AM29LV160D：3.0V CMOS 16MB Boot Sector Flash Memory with Low Power and Flexible Sectors

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AM29LV160D是一款由AMD生产的高性能CMOS 3.0伏特仅有的Boot Sector Flash Memory，适用于2Mx8-Bit和1Mx16-Bit的存储配置。这款芯片的主要特点包括： 1. 单电源操作：AM29LV160D可以在2.7到3.6伏特的电压范围内进行读写操作，特别适合于电池供电的应用场景，同时也兼容对高性能要求的3.3伏特微处理器。 2. 制造工艺先进：采用0.23微米的生产工艺技术，这使得其在性能上表现出色，与0.32微米的Am29LV160B设备完全兼容。 3. 高速访问：具有出色的性能，其访问时间最快可达70纳秒，这对于需要快速数据传输的系统来说是非常重要的。 4. 能效出色：在5兆赫兹工作频率下，它具有极低的功耗，典型值包括自动睡眠模式下的200纳安电流、待机模式下的200纳安电流、读取时的9毫安电流以及编程/擦除操作时的20毫安电流。 5. 灵活的存储结构：AM29LV160D提供了多种存储选择，包括一个16千字节（KB）、两个8KB、一个32KB的字节模式块，以及三十一个64KB的块。此外，还支持一个8千字（Kword）、两个4K字和一个16K字的单词模式，为不同的应用需求提供了极大的灵活性。 6. 动态更新特性：该数据表强调了AMD对产品规格的持续更新，确保了信息的时效性和准确性，用户可以依赖于最新的修订版或修改以适应技术规格的变化。 AM29LV160D是一款设计用于高效率、低功耗环境下的存储解决方案，其独特的电源管理、快速存取速度和多模式存储结构使其在众多电子系统设计中具有广泛的应用潜力。随着技术的不断发展，它将不断适应市场需求并提供稳定可靠的服务。

Am29LV160D 9

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. Table 1 lists the device bus operations, the

inputs and control levels they require, and the resulting

output. The following subsections describe each of

these operations in further detail.

Table 1. Am29LV160D Device Bus Operations

Legend:

L = Logic Low = V

, H = Logic High = V

, V

= 12.0

0.5 V, X = Don’t Care, A

= Address In, D

= Data In, D

OUT

= Data Out

Notes:

1. Addresses are A19:A0 in word mode (BYTE# = V

), A19:A-1 in byte mode (BYTE# = V

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to V

. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

main at V

. The BYTE# pin determines whether the de-

vice outputs array data in words or bytes.

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs pro-

duce valid data on the device data outputs. The device

remains enabled for read access until the command

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to Figure 13 for the timing diagram. I

CC1

the DC Characteristics table represents the active cur-

rent specification for reading array data.

Operation CE# OE# WE# RESET#

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

= V

BYTE#

= V

Read L L H H A

OUT

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write L H L H A

Standby

0.3 V

X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z

Reset X X X L X High-Z High-Z High-Z

Sector Protect (Note 2) L H L V

Sector Address,

A6 = L, A1 = H,

A0 = L

Sector Unprotect (Note 2) L H L V

Sector Address,

A6 = H, A1 = H,

A0 = L

Temporary Sector

Unprotect

XXX V

High-Z

10 Am29LV160D

Writing Commands/Command Sequences

To write a command or command sequence (which

includes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to V

, and OE# to V

For program operations, the BYTE# pin determines

whether the device accepts program data in bytes or

words. Refer to “Word/Byte Configuration” for more

information.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are

required to program a word or byte, instead of four. The

“Word/Byte Program Command Sequence” section

has details on programming data to the device using

both standard and Unlock Bypass command

sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Tables 2 and 3 indicate the

address space that each sector occupies. A “sector

address” consists of the address bits required to

uniquely select a sector. The “Command Definitions”

section has details on erasing a sector or the entire

chip, or suspending/resuming the erase operation.

After the system writes the autoselect command

sequence, the device enters the autoselect mode. The

system can then read autoselect codes from the

internal register (which is separate from the memory

array) on DQ7–DQ0. Standard read cycle timings apply

in this mode. Refer to the “Autoselect Mode” and

“Autoselect Command Sequence” sections for more

information.

CC2

in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and I

read specifications apply. Refer to “Write Operation

Status” for more information, and to “AC Characteris-

tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# pins are both held at V

0.3 V.

(Note that this is a more restricted voltage range than

.) If CE# and RESET# are held at V

, but not within

0.3 V, the device will be in the standby mode, but

the standby current will be greater. The device requires

standard access time (t

) for read access when the

device is in either of these standby modes, before it is

ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the

operation is completed.

In the DC Characteristics table, I

CC3

and I

CC4

repre-

sents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device

energy consumption. The device automatically enables

this mode when addresses remain stable for t

ACC

+ 30

ns. The automatic sleep mode is independent of the

CE#, WE#, and OE# control signals. Standard address

access timings provide new data when addresses are

changed. While in sleep mode, output data is latched

and always available to the system. I

CC4

in the DC

Characteristics table represents the automatic sleep

mode current specification.

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