FT2232的手册，USB接口转换模块。这个模块是单通道的。

FT2232

USB

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Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 2.05

Clearance No.: FTDI#77

Pin No. Name Type Description

2 OSCI

INPUT

Oscillator input.

3 OSCO

OUTPUT

Oscillator output.

6 REF

INPUT

Current reference – connect via a 12KΩ resistor @ 1% to GND.

7 DM

INPUT

USB Data Signal Minus.

INPUT

USB Data Signal Plus.

13 TEST

INPUT

IC test pin – for normal operation should be connected to GND.

14 RESET#

INPUT

Reset input (active low).

60 PWREN#

OUTPUT

Active low power-enable output.

PWREN# = 0: Normal operation.

PWREN# =1 : USB SUSPEND mode or device has not been

configured.

This can be used by external circuitry to power down logic when

device is in USB suspend or has not been configured.

36 SUSPEND#

OUTPUT

Active low when USB is in suspend mode.

59 PWRSAV#

INPUT

USB Power Save input. This is an EEPROM configurable option

used when the FT2232H is used in a self powered mode and is

used to prevent forcing current down the USB lines when the host

or hub is powered off.

PWRSAV# = 1 : Normal Operation

PWRSAV# = 0 : FT2232H forced into SUSPEND mode.

PWRSAV# can be connected to GND (via a 10KΩ resistor) and

another resistor (e.g. 4K7) connected to the VBUS of the USB

connector. When this input goes high, then it indicates to the

FT2232H that it is connected to a host PC. When the host or hub

is powered down then the FT2232H is held in SUSPEND mode.

Table 3.2 Common Function pins

Pin No.

Name Type Description

EECS I/O EEPROM – Chip Select. Tri-State during device reset.

EECLK OUTPUT

Clock signal to EEPROM. Tri-State during device reset. When not in reset,

this outputs the EEPROM clock.

EEDATA

I/O EEPROM – Data I/O Connect directly to Data-In of the EEPROM and to

Data-Out of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the

EEPROM to VCC via a 10K resistor for correct operation. Tri-State during

device reset.

Table 3.3 EEPROM Interface Group

Document No.: FT_000061

FT2232H DUAL HIGH SPEED USB TO MULTIPURPOSE UART/FIFO IC

Datasheet Version 2.05

Clearance No.: FTDI#77

3.4.2 FT2232H pins used in an FT245 Style Synchronous FIFO Interface

The FT2232H only channel A can be configured as a FT245 style synchronous FIFO interface. When

configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.5. To

enter this mode the external EEPROM must be set to make port A 245 mode. A software command (Set

Bit Mode option) is then sent by the application to the FTDI driver to tell the chip to enter single channel

synchronous FIFO mode. In this mode the ‘B’ channel is not available as all resources have been switched

onto channel A. In this mode, data is written or read on the rising edge of the CLKOUT.

Channel A

Pin No.

Name Type FT245 Configuration Description

24,23,22,21,

19,18,17,16

ADBUS[7:0] I/O

D7 to D0 bidirectional FIFO data. This bus is normally input

unless OE# is low.

RXF# OUTPUT

When high, do not read data from the FIFO. When low, there is

data available in the FIFO which can be read by driving RD#

low. When in synchronous mode, data is transferred on every

clock that RXF# and RD# are both low. Note that the OE# pin

must be driven low at least 1 clock period before asserting RD#

low.

TXE# OUTPUT

When high, do not write data into the FIFO. When low, data can

be written into the FIFO by driving WR# low. When in

synchronous mode, data is transferred on every clock that TXE#

and WR# are both low.

RD# INPUT

Enables the current FIFO data byte to be driven onto D0...D7

when RD# goes low. The next FIFO data byte (if available) is

fetched from the receive FIFO buffer each CLKOUT cycle until

RD# goes high.

WR# INPUT

Enables the data byte on the D0...D7 pins to be written into the

transmit FIFO buffer when WR# is low. The next FIFO data byte

is written to the transmit FIFO buffer each CLKOUT cycle until

WR# goes high.

CLKOUT OUTPUT

60 MHz Clock driven from the chip. All signals should be

synchronized to this clock.

OE# INPUT

Output enable when low to drive data onto D0-7. This should be

driven low at least 1 clock period before driving RD# low to

allow for data buffer turn-around.

30 SIWU INPUT

The Send Immediate / WakeUp signal combines two functions

on a single pin. If USB is in suspend mode (PWREN# = 1) and

remote wakeup is enabled in the EEPROM , strobing this pin

low will cause the device to request a resume on the USB Bus.

Normally, this can be used to wake up the Host PC.

During normal operation (PWREN# = 0), if this pin is strobed

low any data in the device TX buffer will be sent out over USB

on the next Bulk-IN request from the drivers regardless of the

pending packet size. This can be used to optimize USB transfer

speed for some applications. Tie this pin to VCCIO if not used.

Table 3.5 Channel A FT245 Style Synchronous FIFO Configured Pin Descriptions

For a functional description of this mode, please refer to section 4.4 FT245 Synchronous FIFO Interface

Mode Description

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