TI FPD-Link III系统设计指南：DS90UB953-Q1与DS90UB954-Q1应用

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本资源是一份由TI（Texas Instruments）发布的应用报告，标题为《如何使用DS90UB953-Q1和DS90UB954-Q1设计FPD-Link III系统》，发布日期为2019年3月，修订于同年6月。这份文档主要关注在汽车行业的高级驾驶辅助系统(ADAS)中，如何有效地设计和实现FPD-Link III接口，这是一种支持高速信号传输的关键技术。首先，概述部分介绍了FPD-Link III设备，如DS90UB95x-Q1，在ADAS系统中的应用及其复杂性，强调了设计过程中的重要性，确保系统的正确实施。设计的目标是系统化地构建一个完整的串行外设接口(SERDES)系统，包括DS90UB953-Q1和DS90UB954-Q1两个核心组件。在基本设计规则部分，作者详细指导了以下几个关键步骤： 1. **IDX和MODE引脚验证**：这是确保电路正常工作的基础，通过检查IDX和MODE引脚的设置，可以确认设备进入正确的工作模式，以便进行有效的数据传输。 2. **成功的I2C通信**：I2C通信是设备间数据交互的重要方式，这里着重介绍了如何通过I2C与DS90UB953-Q1和DS90UB954-Q1进行有效通信，以验证连接和配置的正确性。 3. **I2C passthrough验证**：此部分讲解了如何利用I2C passthrough功能，使得外部设备可以直接访问连接的器件，增强了系统的灵活性和兼容性。 4. **基本诊断和错误寄存器**：这些寄存器用于监测系统状态和错误，提供了实时故障检测和诊断的能力，对系统稳定性和可靠性至关重要。设计FPD-Link之间的SER（串行接收端）和DES（串行发送端）连接时，文档进一步探讨了以下内容： - **回程通道配置**：这部分可能涉及线路阻抗、电源管理等，确保双向通信的完整性。 - **BIST（ Built-in Self-Test）**：内置自测试功能用于在系统运行时检查硬件的性能，保证信号质量和功能一致性。 - **AEQ（Analog Equalization）**：调整模拟均衡器参数以优化信号质量，防止信号失真或衰减，这对高速信号传输的精确性至关重要。这份文档深入浅出地指导了设计师如何运用DS90UB953-Q1和DS90UB954-Q1设计FPD-Link III系统，特别关注了信号处理、通信验证和系统级功能实现，是汽车电子工程师在设计ADAS系统时不可多得的参考资料。通过阅读和实践文档提供的Python源代码，开发者可以更轻松地调试和优化他们的开发板，确保系统性能达到预期标准。

2× 80(f )×(32 / 40)

CSI Throughput 160(25M)×(32 / 40)

= = = 800Mbps

Lane 4 4

CSI Throughput = 2× 80(f )×(32 / 40) = 160(25M)×(32 / 40) = 3.2 Gbps

FC Rate = 2×80(f ) = 160(25M) = 4 Gbps

BC Rate = 2(f ) = 2(25M) = 50 Mbps

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Basic Design Rules

SNLA267A–March 2019–Revised June 2019

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How to Design a FPD-Link III System Using DS90UB953-Q1 and

DS90UB954-Q1

The third mode, non-synchronous internal clocking mode, the serializer uses the internal Always on Clock

(AON) as the reference clock for the forward channel. The OSCCLK_SEL select must be asserted

0x05[3]=1 to enable maximum data rate when using internal clock mode, and the CLK_OUT function is

disabled. A separate reference is provided to the image sensor or ISP. When in CSI-2 mode, the CSI-2

interface may be synchronous to this clock. The CSI-2 rate must be lower than the line rate. For example,

with the internal clock of 24.2 MHz the FPD-Link III forward channel rate is 3.872 Gbps, the CSI-2

throughput must be ≤ 3.1 Gbps (See Table 5).

2.1.1.4 CSI Throughput

When calculating CSI throughput, it is important to account for the extra 8 bits in the 40-bit forward

channel payload that are used for redundancy, parity, check sum, DC balancing, embedded clock, control,

and error checking. A normal CSI payload is 32 bits, and adding these 8 bits will reduce the actual amount

of data that is transferred. This is why 4.16 Gbps of data transfer is actually a maximum of 3.32 Gbps of

CSI throughput.

Because there are four data lanes available, the maximum value of CSI throughput per lane is calculated

as 832 Mbps after dividing the maximum possible CSI throughput by 4. Even if two lanes in use, the

maximum throughput is still divided 4. As a result, the maximum CSI throughput is 832 Mbps, regardless

of how many lanes are used. Note that this is a limitation of the serializer and not the deserializer. This

information is found in Table 5.

2.1.1.5 Clocking and Frequency Selection Example

Using the correct resistor divider values at the MODE pin, the device will power up in synchronous mode.

REFCLK (f0) is 25 MHz, which is the recommended value. Use Table 5 for reference. To calculate the

CLK_OUT, see Section 4.2.

954 Back Channel Bit Rate:

(1)

953 Forward Channel Bit Rate:

(2)

953 CSI Throughput:

(3)

CSI Throughput per Lane:

(4)

Table 5. Mode Clock Calculation Table

MODE

953 CLK_IN

(MHz)

954

REFCL

K (MHz)

954 BC

RATE

(Mbps)

953 FORWARD

(FC) RATE

(Mbps)

953 CSI

THROUGHPUT

MAX CSI

THROUGHPUT

MAX

CSI/LANE

CLK_OUT

Synchronous NA fo 2 × fo fo × 160

≤ fo × 160 ×

32/40

3.32 Gbps 832 Mbps

FC / HS_CLK_DIV) ×

(M/N)

Non Sync

CLK_IN

f1 /

CLKIN_DIV

NA 10 Mbps

f1 × 80 ≤ f1 × 80 × 32/40 3.32 Gbps 832 Mbps

FC / HS_CLK_DIV) ×

(M/N)

f2 /

CLKIN_DIV

f2 × 40 ≤ f2 × 40 × 32/40 3.32 Gbps 832 Mbps

FC / HS_CLK_DIV) ×

(M/N)

Non Sync

AON

NA NA 10 Mbps f3 × 80 ≤ f3 × 80 × 32/40 3.32 Gbps 832 Mbps N/A

Table 6. Mode Clock Settings With Descriptions of fo and f1

POSSIBLE RANGE (MHz) DIVIDE

fo 24 to 26 N/A

f1 25 to 52 for CLKIN_DIV = 1

Basic Design Rules

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How to Design a FPD-Link III System Using DS90UB953-Q1 and

DS90UB954-Q1

Table 6. Mode Clock Settings With Descriptions of fo and f1 (continued)

POSSIBLE RANGE (MHz) DIVIDE

f2 50 to 104 for CLKIN_DIV = 2

f3 48.4 to 51

for CLKIN_DIV = 1, OSCCLK_SEL

= 1

2.2 Successful I

C Communication With 953 and 954

1. Read Device ID of derserializer and serializer locally.

• On both the 953 and 954, register 0x00 contains the I2C_DEVICE_ID that is necessary for I

communication. Communicating locally does not require transactions across the bidirectional

control channel (BCC), which means I

C commands are made directly to the device.

• Using the device ID that is established by the IDX pin, use a read command to access the value in

value returned was different than expected, see Section 2.1 about verifying the IDX pin. If the

value returned was zero, then communication to the device may not be functioning properly.

• The Python code used in Analog Launch Pad (ALP) for this operation is represented below where

the 954_ID is the 8-bit address assigned by the IDX pin, 0x00 is the address where the read will

occur, and 1 is number of bytes returned after the read command occurs:

board.ReadI2C(954_ID,0x00,1)

2. Verify that the deserializer and serializer are locked.

• The LOCK status serves the purpose of validating the link integrity of the connection between the

SER and DES. When the LOCK status is high, the PLL in the DES is locked and validates the data

and clock recovered from the serial input.

Note that the deserializer and serilaizer may not be locked in the beginning stages of bringing up

the system. As a result, continue to check the basic design rules and verify that they are correct.

• On the 954, the DEVICE_STS can be found in register 0x04. Bit [2] holds the lock status of the

device. In addition to the lock status, the device status holds many status flags regarding the

reference clock, pass, power-up initialization, and check sum configuration. A healthy link between

the SER and DES is indicated by the value 0xCF.

3. Read the Device ID of serializer using the deserializer.

• After using I

C locally and verifying a lock between devices, the next step is to send a transaction

over the BCC and verify that it works. A basic way to do this is to read the SER ID using the DES

which is found in register 0x5C on the 954.

• To read the device ID of the SER from the DES, the Alias ID must be used for I

C transactions.

Simply reading register 0x00 of the SER Alias ID should return the value set by the IDX pin. For

more information about aliasing, see Section 2.2.1.

2.2.1 Aliasing

Device Alias ID refers to the alternate 7-bit address assigned to either the serializer, deserializer, or

remote slave. The Device Alias can help differentiate devices that have the same Device ID or physical

C address. TI recommends that the I

C master always use the device alias to communicate with a

remote I

C slave.

For example, the DS90UB954-Q1 can support two serializers like the DS90UB953-Q1. If both serializers

are 953s that house the same camera, the device IDs and default alias IDs for the corresponding devices

will be the same. As a result, the best practice is to write a unique alias ID to each device. Note that these

conventions only apply when the I

C passthrough is enabled. Refer to Section 2.3 on I

C passthrough for

more information.

C addresses are always 7 bits (binary). The majority of the registers on the DS90UB95x-Q1 associated

with I

C addresses uses bits [7:1] for the address, and bit 0 is either reserved or used for some other

purpose. Therefore, while loading an address value to a specific register, it is always left-shifted by 1 bit.

For example, 0x50 (101 0000) left-shifted by 1 bit is 0xA0 (1010 0000). This operation can be represented

as, 0x50<<1 which is equal to 0xA0.

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Basic Design Rules

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How to Design a FPD-Link III System Using DS90UB953-Q1 and

DS90UB954-Q1

Table 7. Bit Description of SER_ALIAS_ID Register With Example

ADDR. 0x5C[7:1] 0x5C[0]

Bits 101 0000 0

Dec. Remote SER Alias ID Automatically Acknowledges I2C writes to

SER

If a defined alias ID does not follow this convention, problems can arise. For example, register 0x5C on

the 954 holds the SER_ALIAS_ID. If bit [0] of the 8-bit address is set to 1, transactions using this alias ID

will be automatically acknowledged. As a result, the controller (or master) sends the slave address and

does not listen for a response from the slave when communicating with the serializer on the bus. All writes

are attempted regardless of the forward channel lock state or status of the remote Serializer Acknowledge.

This can be problematic when validating the link between the SER and DES.

2.2.2 Port Selection on 954

Figure 7. Illustration of Two Ports

The DS90UB954-Q1 has two ports (Port 0 and Port 1) that allow the user to interface two serializers—and

subsequently, two image sensors—with one 954. As a result, the entire register space for Port 0 is similar

but independent to Port 1. Therefore, the port must be accounted for when doing read or write commands

to registers on the 954.

The FPD3_PORT_SEL register, with address of 0x4C, has the ability to control which port is read and

which port has permission to write. Specifically, bit [4] controls which port is read where 0 indicates that

read commands access port 0 and 1 indicates that read commands access port 1. Finally, bits [1] and [0]

control write permissions for port 1 and port 0, respectively. Any combination of RX port registers can be

written simultaneously. This is summarized in Table 8.

Broadcast mode refers to writing both to the port 0 and port 1 serializers simultaneously. This can

achieved by defining both alias IDs to be the same and enabling writes to both ports.

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