![](https://csdnimg.cn/release/download_crawler_static/87603707/bg4.jpg)
BL24C32AA0 32Kbits (4,096×8)
BL24C32AA0 32Kbits (4,096×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited 4 / 17
©2021 Belling All Rights Reserved www.belling.com.cn
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any
other command (see Figure 3).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. (see Figure 3).
Figure 3. Start and Stop Definition
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock
cycle.
SCL
DATA IN
DATA OUT
START
ACKNOWLEDGE
1 8 9
Figure 4. Output Acknowledge
STANDBY MODE: The BL24C32AA0 features a low-power standby mode which is enabled:
(a) upon power-up
(b) after the receipt of the STOP bit and the completion of any internal operations.
MEMORY RESET: After the protocol is interrupted, power loss or system reset, any two-wire part can be reset
by following these steps:
1. Clock up to 9 cycles.
2. Lock SDA high in each cycle while SCL is high.
3. Create a start condition.