Serial ATA Rev 2.6：高速串行接口与NATIVE COMMAND QUEUING技术详解

5星 · 超过95%的资源需积分: 5 183 浏览量更新于2024-09-26 收藏 7.37MB PDF 举报

Serial ATA Revision 2.6 是一项重要的技术规范，它定义了高速序列化的ATA数据链路接口，该接口包括物理层(Phy)、链路层(Link)、传输层(Transport)和应用层(Application)，旨在提升数据传输速度和效率。这个规范基于ATA/ATAPI-6标准，并扩展了针对序列化接口优化的原生命令队列(Native Command Queuing, NCQ)功能。 SATA（Serial Advanced Technology Attachment）是一个用于连接计算机存储设备（如硬盘驱动器）的标准接口，通过串行方式提供更高的带宽和更少的电缆需求，相较于早期并行接口有显著优势。在Serial ATA Revision 2.6中，加入了对NCQ的支持，这是一种允许控制器一次发送多个指令到硬盘的技术，从而提高数据处理能力，减少硬盘寻道时间，显著提升系统性能。 Serial ATA International Organization（SATA-IO）是负责维护和推广Serial ATA标准的机构，参与制定此规范的公司包括Dell Computer Corporation、Hewlett-Packard Corporation、Hitachi Global Storage Technologies, Inc.、Intel Corporation和Seagate Technology等业界巨头。这些公司共同确保了标准的先进性和兼容性。值得注意的是，此规格提供了“按现状”提供，没有任何形式的保证，包括对适销性、非侵权性和特定用途适用性的保证。作者和SATA-IO不承担因使用或实现本规范中的信息而引起的任何侵犯版权或其他产权的责任。接受规格并不意味着获得了使用中的任何许可，也不构成任何形式的默示禁止或授权。 Serial ATA Revision 2.6是现代计算机硬件设计中不可或缺的一部分，它通过标准化和优化的数据传输协议，推动了存储技术的发展，提高了系统的整体性能和用户体验。对于IT专业人士来说，理解和掌握这一规范对于设计和优化存储系统具有重要意义。

Figure 217 – Device Activity LEDs with Separate Wires............................................................. 493

Figure 218 – Device Activity LEDs with Ribbon Cable................................................................ 494

Figure 219 – Device Activity LEDs in a Storage Subsystem....................................................... 495

Figure 220 – Software reset to control port result values............................................................ 496

Figure 221 – Port Multiplier Signature ......................................................................................... 498

Figure 222 – SActive register definition....................................................................................... 504

Figure 223 – SNotification register definition............................................................................... 505

Figure 224 – Error handling architecture..................................................................................... 507

Figure 225 – Port Multiplier Overview ......................................................................................... 517

Figure 226 – Port Selector Overview........................................................................................... 547

Figure 227 – Example Failover Application with Two Hosts ....................................................... 548

Figure 228 – Port selection signal based on assertion of COMRESET to assertion of following

COMRESET ........................................................................................................................ 550

Figure 229 – Complete port selection signal consisting of two sequences with requisite inter-reset

spacings............................................................................................................................... 551

Figure 230 – Control State Machine............................................................................................ 553

Figure 231 – Phy Block Diagram................................................................................................. 554

Figure 232 – Concept summary interconnect structure .............................................................. 584

Figure 233 – An example of signal connections with one I/O Controller..................................... 585

Figure 234 – Example of signal connections with two I/O Modules ............................................ 587

Figure 235 – High Speed Channels – Configuration 0................................................................ 588

Figure 236 – High-Speed Channels – Configuration 1 ............................................................... 588

Figure 237 – Low Speed Channels ............................................................................................. 589

Figure 238 – Interconnect Channels ........................................................................................... 589

Figure 239 – I/O Controller Module Connector Rendering.......................................................... 590

Figure 240 – Connector Pin Layout and Pin Lengths.................................................................. 591

Figure 241 – I/O Controller Module Connector Receptacle Engineering Drawing...................... 592

Figure 242 – Side View of Connector.......................................................................................... 592

Figure 243 – I/O Controller Module Connector Locations on 1xWide I/O module ...................... 594

Figure 244 – I/O Controller Module Connector Locations on 2xWide I/O Module ...................... 595

Serial ATA Revision 2.6 xix

TABLE OF TABLES

Table 1 – State Table Cell Description .......................................................................................... 41

Table 2 – Usage Model Descriptions............................................................................................. 46

Table 3 – Signal and Power SATA Plug and Nominal Mate Sequence ........................................ 76

Table 4 – Allowed values for dimension A and B for device-to-backplane mating ....................... 85

Table 5 – Housing and contact electrical parameters, test procedures, and requirements .......... 89

Table 6 – Mechanical test procedures and requirements ............................................................. 90

Table 7 – Environmental parameters, test procedures, and requirements ................................... 91

Table 8 – Additional requirement................................................................................................... 91

Table 9 – Connector test sequences............................................................................................. 92

Table 10 – Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence ............. 113

Table 11 – Unique Connector Mechanical Testing Procedures and Requirements ................... 114

Table 12 – Slimline Connector Location References .................................................................. 116

Table 13 – Slimline Device plug connector pin definition ............................................................ 121

Table 14 – Slimline Connector Mechanical Test Procedures And Requirements ...................... 128

Table 15 – Multilane Pin Assignments ........................................................................................ 142

Table 16 – Internal Cable / Connector Measurement Parameter and Requirements................. 146

Table 17 – External Single Lane Cable / Connector Measurement Parameter and Requirements

............................................................................................................................................. 146

Table 18 – Limited External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 147

Table 19 – Extended External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 147

Table 20 – Common Interconnect Measurement Procedure Methodologies.............................. 150

Table 21 – Interconnect Test Methodologies / Procedures......................................................... 151

Table 22 – Power segment pin P11 activity signal electrical parameters ................................... 157

Table 23 – Host activity signal electrical parameters .................................................................. 157

Table 24 – Activity signal functional states.................................................................................. 158

Table 25 – Host staggered spin-up control electrical requirements ............................................ 159

Table 26 – Comparator voltages for alternate example presence detection circuit .................... 162

Table 27 – General Specifications............................................................................................... 173

Table 28 – Transmitter Specifications ......................................................................................... 174

Table 29 – Transmitted Signal Requirements ............................................................................. 175

Table 30 – Receiver Specifications ............................................................................................. 177

Table 31 – Lab-Sourced Signal (for Receiver Tolerance Testing) .............................................. 178

Table 32 – OOB Specifications ................................................................................................... 180

Table 33 – Low Transition Density Pattern (LTDP) Starting with RD- ........................................ 199

Table 34 – Low Transition Density Pattern (LTDP) starting with RD+ ........................................ 200

Table 35 – High Transition Density Pattern (HTDP) Starting with RD– ...................................... 201

Table 36 – High Transition Density Pattern (HTDP) Starting with RD+ ...................................... 201

Table 37 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD– ..................... 202

Table 38 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD+..................... 203

Table 39 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD– ....................... 204

Table 40 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD+ ....................... 204

Table 41 – Lone-Bit Pattern (LBP) Starting with RD– ................................................................. 205

Table 42 – Lone-Bit Pattern (LBP) Starting with RD+ ................................................................. 205

Table 43 – Composite-Bit Pattern (COMP) Starting with RD–.................................................... 206

Table 44 – Composite-Bit Pattern (COMP) Starting with RD+.................................................... 208

Table 45 – Frame Error Rate Confidence Levels Versus Sample Size ...................................... 225

Table 46 – Bit Error Rate Confidence Levels Versus Sample Size ............................................ 226

Table 47 – OOB Signal Times..................................................................................................... 263

Table 48 – Interface Power States .............................................................................................. 273

Table 49 – State Diagram Host Phy Initialization State Machine................................................ 275

Table 50 – State Diagram Device Phy Initialization State Machine ............................................ 279

Table 51 – Bit Designations......................................................................................................... 290

Table 52 – Conversion Examples................................................................................................ 291

Table 53 – 5B/6B Coding ............................................................................................................ 293

Table 54 – 3B/4B Coding ............................................................................................................ 293

Table 55 – Encoding Examples................................................................................................... 294

Table 56 – Valid Data Characters ............................................................................................... 295

Table 57 – Valid Control Characters ........................................................................................... 299

Table 58 – Single Bit Error with Two Character Delay ................................................................ 301

Table 59 – Single Bit Error with One Character Delay ................................................................ 301

Table 60 – Description of Primitives ............................................................................................ 303

Table 61 – Primitive Encoding..................................................................................................... 304

Table 62 – CONT

Usage Example ............................................................................................ 306

Table 63 – Example of Components of a Round Trip Delay....................................................... 309

Table 64 – SRST Write from Host to Device Transmission Breaking Through a Device to Host

Data FIS............................................................................................................................... 310

Table 65 – Command Shadow Register Block Register Transmission Example ....................... 310

Table 66 – Data from Host to Device Transmission Example..................................................... 311

Table 67 – State Diagram Link Idle ............................................................................................. 314

Table 68 – State Diagram Link Transmit..................................................................................... 317

Table 69 – State Diagram Link Receive ...................................................................................... 324

Table 70 – State Diagram Link Power Mode............................................................................... 330

Table 71 – Simplified Shadow Register Block register numbering ............................................. 336

Table 72 – BIST Activate FIS Modes and Bit Settings ................................................................ 347

Table 73 – IDENTIFY DEVICE information ................................................................................. 433

Table 74 – IDENTIFY PACKET DEVICE information ................................................................. 439

Table 75 – SCR definition............................................................................................................ 500

Table 76 – SCR Definition ........................................................................................................... 500

Table 77 – State Diagram Collisions ........................................................................................... 521

Table 78 – State Diagram Hot Plug State Machine for Host Port ............................................... 523

Table 79 – State Diagram Hot Plug State Machine for Device Port............................................ 525

Table 80 – Register Values for an Unsupported Command ....................................................... 528

Table 81 – Static Information Registers ...................................................................................... 530

Table 82 – Status Information and Control Registers ................................................................. 532

Table 83 – Features Supported Registers .................................................................................. 536

Table 84 – Features Enabled Registers ...................................................................................... 537

Table 85 – Vendor Unique Registers .......................................................................................... 538

Table 86 – Phy Event Counter Registers .................................................................................... 539

Table 87 – Reserved Registers ................................................................................................... 539

Table 88 – PSCR Definition......................................................................................................... 540

Table 89 – READ PORT MULTIPLIER Command Definition ..................................................... 540

Table 90 – READ PORT MULTIPLIER Success Status Result Values ...................................... 541

Table 91 – READ PORT MULTIPLIER Error Status Result Values............................................ 542

Table 92 – WRITE PORT MULTIPLIER Command Definition .................................................... 542

Table 93 – WRITE PORT MULTIPLIER Success Status Result Values .................................... 543

Table 94 – WRITE PORT MULTIPLIER Error Status Result Values .......................................... 544

Table 95 – Port selection signal inter-reset timing requirements ................................................ 550

Table 96 – CRC and scrambler calculation example - PIO Write Command ............................. 570

Table 97 – J1, J2, J3 Pin Assignments ....................................................................................... 596

Table 98 – J4, J5, J6 Pin Assignments ....................................................................................... 596

剩余599页未读，继续阅读

hongye299

粉丝: 2
资源: 28

Serial ATA Rev 2.6：高速串行接口与NATIVE COMMAND QUEUING技术详解

SerialATA_Revision_3_3_Gold

SerialATA_SPEC_Revision_3_1_Gold.pdf

Serial ATA Specification Rev. 2.6

Serial ATA Revision 2.6 规范详解

Serial ATA Revision 3.0

Serial ATA 2.6：高速串行ATA规范

Serial ATA 2.6协议规范详解

Serial ATA 2.6规范详解：高速串行ATA接口技术

SerialATA-Revision-2-6.pdf

SerialATA_Revision_2_6_Gold

最新资源