TI DRV2604L：LRA和ERM触觉驱动器，带智能环路架构

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"TI-DRV2604L是一款由德州仪器(TI)推出的专为LRA(线性谐振致动器)和ERM(偏轴转动惯量电机)设计的2V至5.2V触觉驱动器。该芯片集成了内部存储器和智能环路架构，提供灵活的触觉和振动驱动功能。" 【TI DRV2604L】是德州仪器的一款高效触觉驱动器，它支持LRA和ERM两种类型的触觉反馈装置。该芯片的核心特性在于其内置的数字回放引擎，可以通过I2C接口进行控制，实现对波形序列的精确管理。这个回放引擎包括波形序列器和触发器，可以实现实时回放模式，并且有内部RAM来存储自定义的波形。 TI DRV2604L的一大亮点是其智能环路架构，这是一项正在申请专利的控制算法。这一架构提供了自动过驱动和制动功能，确保了驱动效率和安全性。对于LRA，它还具备自动谐振跟踪和报告能力，有助于优化性能。此外，该芯片还具备自动致动器诊断和自动级别校准功能，能够适应不同型号的致动器，并确保一致的触感体验。该驱动器兼容Immersion TouchSense®3000技术，这意味着它可以无缝集成到采用此技术的系统中。DRV2604L可以应对电池放电过程中的电压变化，进行驱动补偿，保证在低电压环境下仍能保持稳定工作。工作电压范围广泛，从2V到5.2V，使得该芯片适合各种电源条件。它采用高效的差分开关输出驱动，支持脉宽调制(PWM)输入，允许用户通过调整PWM占空比来控制振动强度。此外，还有一个硬件触发输入，可以快速响应外部事件。数字接口与1.8V兼容，并能承受VDD耐压。在应用方面，DRV2604L特别适用于需要高质量触觉反馈的设备，如手机和平板电脑等移动设备，可以提供细腻、真实的触感体验，提升用户体验。 TI DRV2604L是一款高度集成、智能化的触觉驱动解决方案，旨在为LRA和ERM设备提供精确、动态的振动控制，适应各种应用场景，并确保在整个工作电压范围内提供一致的性能。

Input and output

Accleration

Ideal Open-Loop Waveform for Motor A

Output with feedback

Ideal Open-Loop Waveform for Motor B

Same simple input for

both motors

Feedback provides

optimum output drive

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

Feature Description (continued)

An open-loop haptic system typically drives an overdrive voltage at startup that is higher than the steady-state

rated voltage of the actuator to decrease the startup latency of the actuator. Likewise, a braking algorithm must

be employed for effective braking. When using an open-loop driver, these behaviors must be contained in the

input waveform data. Figure 12 shows how two different ERMs with different startup behaviors (Motor A and

Motor B) can both be driven optimally by the smart-loop architecture with a simple input for both motors. The

smart-loop architecture works equally well for LRAs with a combination of feedback control and an auto-

resonance engine.

Figure 12. Waveform Simplification With Smart Loop

8.3.2.4.1 Startup Boost

To reduce the actuator start-time performance, the DRV2604L device has an overdrive boost feature that applies

higher loop gain to transient response of the actuator. The STARTUP_BOOST bit enables the feature.

8.3.2.4.2 Brake Factor

To reduce the actuator brake-time performance, the DRV2604L device provides a means to increase the gain

ratio between braking and driving gain. Higher feedback-gain ratios reduce the brake time, however, the gain

ratios also reduce the stability of the closed-loop system. The FB_BRAKE_FACTOR[2:0] bits can be adjusted to

set the brake factor.

8.3.2.4.3 Brake Stabilizer

To improve brake stability at high brake-factor gain ratios, the DRV2604L device has a brake-stabilizer

mechanism that automatically reduces the loop gain when the braking is near completion. The

BRAKE_STABILIZER bit enables the feature.

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

Feature Description (continued)

8.3.2.5 Automatic Level Calibration

The smart-loop architecture uses actuator feedback by monitoring the back-EMF behavior of the actuator. The

level of back-EMF voltage can vary across actuator manufacturers because of the specific actuator construction.

Auto calibration compensates for the variation and also performs scaling for the desired actuator according to the

specified rated voltage and overdrive clamp-register settings. When auto calibration is performed, a 100% signal

level at any of the DRV2604L input interfaces supplies the rated voltage to the actuator at steady-state. The

feedback allows the output level to increase above the rated voltage level for automatic overdrive and braking,

but without allowing the output level to exceed the programmable overdrive clamp voltage.

In the event where the automatic level-calibration routine fails, the DIAG_RESULT bit in register 0x00 is asserted

to flag the problem. Calibration failures are typically fixed by adjusting the registers associated with the automatic

level-calibration routine or, for LRA actuators, the registers associated with the automatic-resonance detection

engine. See the

器件和文档支持

section for automatic-level calibration programming.

8.3.2.5.1 Automatic Compensation for Resistive Losses

The DRV2604L device automatically compensates for resistive losses in the driver. During the automatic level-

calibration routine, the impedance of the actuator is checked and the compensation factor is determined and

stored in the A_CAL_COMP[7:0] bit.

8.3.2.5.2 Automatic Back-EMF Normalization

The DRV2604L device automatically compensates for differences in back-EMF magnitude between actuators.

The compensation factor is determined during the automatic level-calibration routine and the factor is stored in

the A_CAL_BEMF[7:0] bit.

8.3.2.5.3 Calibration Time Adjustment

The duration of the automatic level-calibration routine has an impact on accuracy. The impact is highly

dependent on the start-time characteristic of the actuator. The auto-calibration routine expects the actuator to

have reached a steady acceleration before the calibration factors are calculated. Because the start-time

characteristic can be different for each actuator, the AUTO_CAL_TIME[1:0] bit can change the duration of the

automatic level-calibration routine to optimize calibration performance.

8.3.2.5.4 Loop-Gain Control

The DRV2604L device allows the user to control how fast the driver attempts to match the back-EMF (and thus

motor velocity) and the input signal level. Higher loop-gain (or faster settling) options result in less-stable

operation than lower loop gain (or slower settling). The LOOP_GAIN[1:0] bit controls the loop gain.

8.3.2.5.5 Back-EMF Gain Control

The BEMF_GAIN[1:0] bit sets the analog gain for the back-EMF amplifier. The auto-calibration routine

automatically populates the bit with the most appropriate value for the actuator.

Modifying the SAMPLE_TIME[1:0] bit also adjusts the back-EMF gain. The higher the sample time, the higher

the gain.

By default, the back-EMF is sampled once during a period. In the event that a twice per-period sampling is

desired, assert the LRA_DRIVE_MODE bit.

8.3.2.6 Actuator Diagnostics

The DRV2604L device is capable of determining whether the actuator is not present (open) or shorted. If a fault

is detected during the diagnostic process, the DIAG_RESULT bit is asserted.

8.3.2.7 Automatic Re-Synchronization

For the LRA, the DRV2604L device features an automatic re-synchronization mode which automatically pushes

the actuator in the correct direction when a waveform begins playing while the actuator is moving. If the actuator

is at rest when the waveform begins, the DRV2604L device drives in the default direction.

DRV2604L

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

www.ti.com.cn

Feature Description (continued)

8.3.3 Open-Loop Operation for LRA

In the event that open-loop operation is desired (such as for off-resonance driving) the DRV2604L device

includes an open-loop LRA drive mode that is available through the PWM input or through the digital interface.

When using the PWM input in open-loop mode, the DRV2604L device employs a fixed divider that observes the

PWM signal and commutates the output drive signal at the PWM frequency divided by 128. To accomplish LRA

drive, the host should drive the PWM frequency at 128 times the desired operating frequency.

When activated, the digital open-loop mode is available for pre-stored waveforms as well as for RTP mode. The

OL_LRA_PERIOD bit in register 0x20 programs the operating frequency, which is derived from the PWM output

frequency, ƒ

O(PWM)

. Use Equation 1 to calculate the driving frequency. The open-loop mode does not receive the

benefits of the smart-loop architecture.

8.3.4 Open-Loop Operation for ERM

The DRV2604L device offers ERM open-loop operation through the PWM input. The output voltage is based on

the duty cycle of the provided PWM signal, where the OD_CLAMP[7:0] bit in register 0x17 sets the full-scale

amplitude. For details see the Rated Voltage Programming section.

8.3.5 Flexible Front-End Interface

The DRV2604L device offers multiple ways to launch and control haptic effects. The MODE[2:0] bit in register

0x01 is used to select the interface mode.

8.3.5.1 PWM Interface

When the DRV2604L device is in PWM interface mode, the device accepts PWM data at the IN/TRIG pin. The

DRV2604L device drives the actuator continuously in PWM interface mode until the user sets the device to

standby mode or to enter another interface mode. In standby mode, the strength of vibration is determined by the

duty cycle.

For the LRA, the DRV2604L device automatically tracks the resonance frequency unless the LRA_OPEN_LOOP

bit in register 0x1D is set. If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the frequency of the

PWM input signal. Specifically, the driving frequency is the PWM frequency divided by 128.

8.3.5.2 Internal Memory Interface

The DRV2604LL device is designed with 2 kB of integrated RAM for waveform storage used by the playback

engine. The data is stored in an efficient way (voltage-time pairs) to maximize the number of waveforms that can

be carried. The playback engine also has the ability to generate smooth ramps (up or down) by relying on the

start-waveform and end-waveform points and by using linear interpolation techniques.

Storing waveforms on the DRV2604LL device instead of the host processor has several advantages including:

• Offloading processing requirements, such as PWM generation, from the host processor or micro-controller

• Improving latency by storing the waveforms on the DRV2604LL device and only requiring a trigger signal

• Reducing I

C traffic by eliminating the requirement to transfer waveform data

8.3.5.2.1 Waveform Sequencer

The waveform sequencer queues waveform identifiers for playback. Eight sequence registers queue up to eight

waveforms for sequential playback. A waveform identifier is an integer value referring to the index position of a

waveform in the RAM library. Playback begins at register address 0x04 when the user asserts the GO bit

(register 0x0C). When playback of that waveform ends, the waveform sequencer plays the waveform identifier

held in register 0x05 if the next waveform is non-zero. The waveform sequencer continues in this way until it

reaches an identifier value of zero or until all eight identifiers are played (register addresses 0x04 through 0x0B),

whichever scenario is reached first.

The waveform identifier range is 1 to 127. The MSB of each sequence register can implement a delay between

sequence waveforms. When the MSB is high, bits [6:0] indicate the length of the wait time. The wait time for that

step then becomes WAV_FRM_SEQ[6:0] × 10 ms.

DRV2604L

www.ti.com.cn

ZHCSDF4F –MAY 2014–REVISED MARCH 2018

Feature Description (continued)

8.3.5.2.2 Library Parameterization

The RAM waveforms are augmented by the time offset registers (registers 0x0D to 0x10). The augmentation

occurs only for the RAM waveforms and not for the other interfaces (such as PWM and RTP). The purpose of

the functionality is to add time stretching (or time shrinking) to the waveform. This functionality is useful for

customizing the entire library of waveforms for a specific actuator rise time and fall time.

The time parameters that can be stretched or shrunk include:

ODT Overdrive time

SPT Sustain positive time

SNT Sustain Negative Time

BRT Brake Time

The time values are additive offsets and are 8-bit signed values. The default offset of the time values is 0.

Positive values add and negative values subtract from the time value of the effect that is currently played. The

most positive value in the waveform is automatically interpreted as the overdrive time, and the most negative

value in the waveform is automatically interpreted as the brake time. The time-offset parameters are applied to

both voltage-time pairs and linear ramps. For linear ramps, linear interpolation is stretched (or shrunk) over the

two operative points for the period (see Equation 3).

t + t

(ofs)

where

• t

(ofs)

is the time offset (3)

Changing the playback interval can also manipulate the waveforms stored in memory. Each waveform in memory

has a granularity of 5 ms. If the user desires greater granularity, a 1-ms playback interval can be obtained by

asserting the PLAYBACK_INTERVAL bit in register 0x1F.

8.3.5.3 Real-Time Playback (RTP) Interface

The real-time playback mode is a simple, single 8-bit register interface that holds an amplitude value. When real-

time playback is enabled, the real-time playback register is sent directly to the playback engine. The amplitude

value is played until the user sends the device to standby mode or removes the device from RTP mode. The

RTP mode operates exactly like the PWM mode except that the user enters a register value over the I

C rather

than a duty cycle through the input pin. Therefore, any API (application-programming interface) designed for use

with a PWM generator in the host processor can write the data values over the I

C rather than writing the data

values to the host timer. This ability frees a timer in the host while retaining compatibility with the original

software.

For the LRA, the DRV2604L device automatically tracks the resonance frequency unless the LRA_OPEN_LOOP

bit is set (in register 0x1D). If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the open-loop

frequency set in the OL_LRA_PERIOD[6:0] bit in register 0x20.

8.3.5.4 Analog Input Interface

When the DRV2604L device is in analog-input interface mode, the device accepts an analog voltage at the

IN/TRIG pin. The DRV2604L device drives the actuator continuously in analog-input interface mode until the user

sets the device to standby mode or to enter another interface mode. The reference voltage in standby mode is

1.8 V. Therefore, the 1.8-V reference voltage is interpreted as a 100% input value. A reference voltage of 0.9 V

is interpreted as a 50% input value and a reference voltage of 0 V is interpreted as a 0% input value. The input

value in standby mode is analogous to the duty-cycle percentage in PWM mode.

For the LRA, the DRV2604L automatically tracks the resonance frequency unless the LRA_OPEN_LOOP bit is

set (in register 0x1D). If the LRA_OPEN_LOOP bit is set, the LRA is driven according to the open-loop frequency

set in OL_LRA_PERIOD[6:0] bit in register 0x20.

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TI DRV2604L：LRA和ERM触觉驱动器，带智能环路架构

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