TI DIX9211: 216-kHz Digital Audio Interface Transceiver

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"TI-DIX9211.pdf是一款216-kHz数字音频接口收发器，适用于家庭影院、AV接收设备、电视、音响条、高保真声卡及音乐录制和广播等领域。" TI-DIX9211是德州仪器(TI)推出的一款高性能数字音频接口收发器，它具有集成的DIX（数字接口交换）功能和信号路由，能支持多种数字音频格式和控制方式。这款芯片的主要特点包括： 1. **其他功能特性**： - **电源管理**：提供电源下降(Power Down)功能，可通过引脚或寄存器进行控制，实现节能。 - **异步操作**：支持DIR（数字输入接收器）和DIT（数字输出发送器）的异步工作模式。 - **PCM端口采样频率计数器**：用于监测和管理数字音频的采样频率。 - **多路复用和数据路由**：可以对PCM数据进行多路复用和路由，提高系统的灵活性。 - **GPIO和GPO**：通用输入/输出和通用输出引脚，可配置为不同用途。 - **多种数字音频接口支持**：兼容I2S、左对齐、右对齐格式，以及SPI和I2C硬件控制模式。 - **外部晶体振荡器**：内置24.576MHz晶体振荡器，确保高精度时钟源。 2. **数字音频接口接收器(DIR)**： - **高性能接收能力**：能够处理最高24位，216kHz的音频数据，提供高解析度音频输出。 - **低抖动**：50ps的超低抖动，保证了音频信号的高质量传输。 - **非PCM检测**：支持IEC61937、DTS-CD/LD等非PCM音频格式的识别。 3. **电源和工作环境**： - **电源电压**：DIX和所有数字部分均工作在3.3V（2.9V到3.6V）范围内。 - **工作温度范围**：-40°C到+85°C，适应各种环境条件。 4. **应用领域**： - **家庭娱乐系统**：如家庭影院和AV接收机，通过2个同轴S/PDIF输入和10个光纤S/PDIF输入接口，提供丰富的数字音频接入。 - **电视和音响条**：提升电视音频质量，增强音响效果。 - **专业音频设备**：适用于音乐乐器、录音和广播行业的高保真声卡，保证音质无损传输。 5. **数字音频接口发射器(DIT)**： - **高容量传输**：同样支持24位，216kHz的音频数据传输，24位数据长度，确保传输的音频信号完整性。 - **48位通道状态信息**：用于传递音频通道的相关信息，如声道数、采样率等。 TI-DIX9211的这些特性使其成为数字音频设备设计的理想选择，无论是家用娱乐系统还是专业音频设备，都能提供卓越的音频性能和强大的接口兼容性。其紧凑的48引脚LQFP封装也方便在有限的空间内集成。

DIX9211

SBAS519 –SEPTEMBER 2010

www.ti.com

Digital Audio Interface Receiver (RXIN0 to RXIN11)

Input Details for Pins RXIN0 Through RXIN11

Up to 12 single-ended S/PDIF input pins are available. Two of the S/PDIF input pins integrate coaxial amplifiers.

The other 10 pins are designed to be directly connected to CMOS sources or standard S/PDIF optical modules.

Each of the inputs can tolerate 5-V inputs.

The DIR module in the DIX9211 complies with these Digital Audio I/F standards:

• S/PDIF

• IEC60958 (formerly IEC958)

• JEITA CPR-1205 (formerly EIAJ CP-1201/340)

• AES3

• EBU Tech 3250 (also known as AES/EBU)

In addition, the DIR module within the DIX9211 also meets and exceeds jitter tolerance limits as specified by

IEC60958-3 for sampling frequencies between 28 kHz and 216 kHz.

Each of the physical connections used for these standards (optical, differential, and single-ended) have different

signal levels. Care should be taken to ensure that each of the RXIN pins is not overdriven or underdriven, such

as driving a coaxial 0.2-V

signal into a CMOS 3.3-V input.

RXIN0 and RXIN1 integrate coaxial input amplifiers. This architecture means that they can be directly connected

to either coaxial input (or RCA/Phono) S/PDIF sources. They can accept a minimum of 0.2V

. They can also be

connected to maximum 5-V TTL sources, such as optical receivers. (NOTE: Consideration should be made for

electrostatic discharge, or ESD, on the input connectors.)

RXIN2 to RXIN11 are 5-V tolerant TTL level inputs. These inputs are typically used as connections to optical

receiver modules (known as TOSLINK™ connectors).

RXIN8 through RXIN11 are also part of the MPIO_A (Multipurpose Input/Output A) group. These I/O pins can

either be set as S/PDIF inputs, or reassigned to other functions (see the MPIO section). To configure MPIO_A as

S/PDIF inputs, set Register MPASEL[1:0] to '00'.

Typically, no additional components are required to connect an optical receiver to any RXIN pin. However,

consideration should be given to the output characteristics of the specific receiver modules used, especially if

there is a long printed circuit board (PCB) trace between the receiver and the DIX9211 itself.

For differential inputs (such as the AES/EBU standard), differential to single-ended circuitry is required.

Product Folder Link(s): DIX9211

DIX9211

www.ti.com

SBAS519 –SEPTEMBER 2010

PLL Clock Source (Built-in PLL and VCO) Details

The DIX9211 an has on-chip PLL (including a voltage-controlled oscillator, or VCO) for recovering the clock from

the S/PDIF input signal.

The VCO-derived clock is identified as the PLL clock source.

When locked, the onboard PLL generates a system clock that synchronizes with the input biphase signal. When

unlocked, the PLL generates its own free-run clock (from the VCO).

The generated system clocks from the PLL can be set to fixed multiples of the input S/PDIF frequency. Register

30h/PSCK[2:0] can configure the output clock to 128f

, 256f

or 512f

The DIX9211 also has an automatic default output rate that is calculated based on the incoming S/PDIF

frequency. This calculation and rate are controlled by Register 30h/PSCKAUTO. In its default mode, the SCK

dividing ratio is configured according to these parameters:

• 512f

: 54 kHz and below.

• 256f

: 54 kHz to 108 kHz

• 128f

: 108 kHz and above (or unlocked)

PSCKAUTO takes priority over any settings in PSCK[2:0]. PSCK[2:0] only becomes relevant in the system when

the PSCKAUTO Register is set to '0'.

The DIX9211 can decode S/PDIF input signals between sampling frequencies of 7 kHz and 216 kHz for all

PSCK[2:0] settings. The relationship between the output clock (SCKO, BCKO, LRCKO) at the PLL source and

PSCK[2:0] selection is shown in Table 3.

Table 3. SCKO, BCKO and LRCKO Frequency Set by PSCK[2:0]

OUTPUT CLOCK AT PLL SOURCE PSCK[2:0] SETTING

SCKO BCKO LRCKO PSCK2 PSCK1 PSCK0

128f

64f

0 0 0

256f

64f

0 1 0

512f

(1)

64f

1 0 0

(1) 512f

SCK is only supported at 108 kHz or lower sampling frequency of incoming biphase signal.

In PLL mode, the output clocks (SCKO, BCKO, LRCKO) are generated from the PLL source clock.

The relationship between the sampling frequencies (f

) of the input S/PDIF signal and the frequency of LRCKO,

BCKO, and SCKO are shown in Table 4.

Table 4. Output Clock Frequency at PLL Lock State

LRCK BCK SCK (Depends on PSCK[2:0] Setting)

64f

128f

256f

512f

8 kHz 0.512 MHz 1.024MHz 2.048 MHz 4.096 MHz

11.025 kHz 0.7056 MHz 1.4112 MHz 2.8224 MHz 5.6448 MHz

12 kHz 0.768 MHz 1.536 MHz 3.072 MHz 6.144 MHz

16 kHz 1.024 MHz 2.048 MHz 4.096 MHz 8.192 MHz

22.05 kHz 1.4112 MHz 2.8224 MHz 5.6448 MHz 11.2896 MHz

24 kHz 1.536 MHz 3.072 MHz 6.144 MHz 12.288 MHz

32 kHz 2.048 MHz 4.096 MHz 8.192 MHz 16.384 MHz

44.1 kHz 2.8224 MHz 5.6448 MHz 11.2896 MHz 22.5792 MHz

48 kHz 3.072 MHz 6.144 MHz 12.288 MHz 24.576 MHz

64 kHz 4.096 MHz 8.192 MHz 16.384 MHz 32.768 MHz

88.2 kHz 5.6448 MHz 11.2896 MHz 22.5792 MHz 45.1584 MHz

96 kHz 6.144 MHz 12.288 MHz 24.576 MHz 49.152 MHz

128 kHz 8.192 MHz 16.384 MHz 32.768 MHz N/A

176.4 kHz 11.2896 MHz 22.5792 MHz 45.1584 MHz N/A

192 kHz 12.288 MHz 24.576 MHz 49.152 MHz N/A

Product Folder Link(s): DIX9211

FILT

AGND DGND

Charge

Pump

VCO

DIX9211

PLL Section

DIX9211

SBAS519 –SEPTEMBER 2010

www.ti.com

DIR and PLL Loop Filter Details

The DIX9211 incorporates a PLL for generating clocks synchronized with the input biphase signal (S/PDIF). The

onboard PLL requires an external loop filter. The components and configuration shown in Figure 3 and Table 5

are recommended for optimal performance, with these considerations:

• The resistor and capacitors that configure the filter should be located and routed as close as possible to the

DIX9211. The external loop filter must be placed on the FILT pins.

• The GND node of the external loop filter must be directly connected with AGND pin of the DIX9211; it must

be not combined with other signals.

Figure 3 shows the configuration of the external loop filter and the connection with the DIX9211.

Figure 3. Loop Filter Connection

The recommended value of loop filter components is shown in Table 5.

Table 5. Recommended Value of Loop Filter Components

REF. NO. RECOMMENDED VALUE TYPE TOLERANCE

680 Ω Metal film or carbon ≤ 5%

0.068 µF Film or ceramic (CH or C0G) ≤ 5%

0.0047 µF Film or ceramic (CH or C0G) ≤ 5%

External (XTI) Clocks, Oscillators, and Supporting Circuitry

An external clock source (CMOS or crystal/resonator) is known as the XTI source. The XTI source can be either

a CMOS logic source, or a crystal resonator (internal circuitry in the DIX9211 can start the crystal resonating).

Whichever clock source is used, it must be 24.576 MHz.

The DIX9211 uses the XTI source as a reference clock in order to calculate the sampling frequency of the

incoming S/PDIF stream. It is also used as the clock source in XTI clock source mode.

When using a resonator as an XTI source, the following points should be considered:

• The 24.576-MHz resonator should be connected between the XTI and XTO pins

• The resonator should be a fundamental mode type

• A crystal or ceramic resonator can be used as the XTI source

• The values of the load capacitors C

and C

and the current limiting resistor R

all depend on the

characteristics of the resonator

• No external feedback resistor between the XTI and XTO pins is required, because the resistor is integrated

into the device

• No loads other than the resonator should be used on the XTO pin

When using an external oscillation circuit with a CMOS output, the following points should be considered:

• Always supply a 24.576-MHz clock on the XTI pin

• Only 3.3 V is supported on the XTI pin; 5 V is not supported

• XTO should be left floating

Product Folder Link(s): DIX9211

XTI

XTO

Crystal

OSC

Circuit

24.576 MHz

Internal Clock

External

Clock

Must be open

DIX9211

CL1

CL2

XTI

XTO

Crystal

OSC

Circuit

24.576 MHz

Internal Clock

(Optional)

Resonator

DIX9211

Resonator Connection External Clock Input Connection

DIX9211

www.ti.com

SBAS519 –SEPTEMBER 2010

Figure 4 illustrates the connections for the XTI and XTO pins for both a resonator connection and an external

clock input connection.

Figure 4. XTI and XTO Connection Diagram

In XTI mode, the output clocks (SCKO, BCKO, and LRCKO) are generated from the XTI source clock.

using the DIR as a clock source, the XTI source is not required; thus, the internal oscillator can be switched off.

There is a constraint, however, that when the DIR wide mode is being set (for example, in 192-kHz support), the

XTI is always used. The sampling frequency calculator also requires the XTI source.

XMCKO (the XTI clock buffered output) provides a buffered (and divided) XTI clock that can be output to

MPIO_A. Register 24h/XMCKEN controls whether the XMCKO should be muted or not, and Register

24h/XMCKDIV controls the division factor.

DIR Data Description

Decoded Serial Audio Data Output and Interface Format

The DIX9211 supports the following four data formats for the decoded data:

• 16-bit MSB First, Right-Justified

• 24-bit MSB First, Right-Justified

• 24-bit MSB First, Left-Justified

• 24-bit MSB First, I

Decoded data are MSB first and twos complement in all formats.

The format of the decoded data is selected by the RXFMT[2:0] register. The possible data formats are shown in

Table 6.

Table 6. DIR Serial Audio Data Output Format Set by RXFMT[2:0]

RXFMT[2:0] SETTING

DIR SERIAL AUDIO DATA OUTPUT FORMAT RXFMT2 RXFMT1 RXFMT0

24-bit MSB First, Right-Justified 0 0 0

16-bit MSB First, Right-Justified 0 1 1

24-bit MSB First, I

S (Default) 1 0 0

24-bit MSB First, Left-Justified 1 0 1

Product Folder Link(s): DIX9211

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