LPC11C14芯片详解：ARM Cortex-M0微控制器用户手册

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"LPC11C14是NXP公司生产的一款基于ARMCortex-M0内核的微控制器，常用于嵌入式硬件开发。该芯片具有丰富的外设接口和低功耗特性，适用于各种小型、高效能的应用场景。用户手册UM10398详细介绍了LPC11C14的特性和使用方法，涵盖了从基本结构到高级功能的全面内容。" LPC11C14是一款基于ARMCortex-M0处理器的微控制器，属于NXP的LPC11系列。Cortex-M0是ARM公司设计的一种超低功耗、高性能的32位处理器内核，适用于对成本和功耗有严格要求的嵌入式应用。LPC11C14芯片的主要特点是其集成度高，提供了多种外设接口，如GPIO（通用输入输出）、UART（通用异步收发传输器）、SPI（串行外围接口）和I2C（Inter-IntegratedCircuit）等通信协议，以及定时器、ADC（模拟数字转换器）和PWM（脉宽调制）等功能。该用户手册UM10398详细阐述了LPC11C14的硬件架构，包括处理器内核、内存组织、时钟系统、电源管理模块以及各种外设的使用。其中，时钟系统是微控制器性能和功耗的关键，手册中提到了参考时钟作为时钟源的添加，这有助于开发者理解和配置系统时钟以优化性能和能耗。文档还提到了LPC11C14内置的CAN（ControllerAreaNetwork）控制器，这是一种汽车和工业自动化领域常用的通信协议，它支持多主站网络，具有高可靠性。手册新增了对CAN收发器的描述，说明了如何利用这一功能进行网络通信。在软件开发方面，手册更新了系统滴答定时器（SystemTickTimer）的描述，这是ARM Cortex-M系列处理器中的一个关键组件，用于实现操作系统和实时任务调度的定时中断。此外，手册还提及了单周期硬件乘法运算的特性，这对于需要高效算术运算的应用来说是非常重要的。编辑性更新包括对外部中断和中断处理的详细说明，以及对编程模型、调试接口和支持的开发工具的介绍。这些内容对于开发者来说至关重要，可以帮助他们快速理解和掌握LPC11C14的使用，从而高效地进行硬件开发。 LPC11C14是一款面向嵌入式领域的微控制器，通过NXP提供的详细用户手册，开发者可以深入理解其工作原理，并利用其强大的功能进行各种应用的开发。无论是初学者还是经验丰富的工程师，这份手册都是一个宝贵的参考资料。

User manual Rev. 3 — 14 January 2011 16 of 413

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.3 System PLL control register

This register connects and enables the system PLL and configures the PLL multiplier and

divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various

clock sources. The input frequency is multiplied up to a high frequency, then divided down

to provide the actual clock used by the CPU, peripherals, and memories. The PLL can

produce a clock up to the maximum allowed for the CPU.

3.5.4 System PLL status register

This register is a Read-only register and supplies the PLL lock status (see

Section 3.10.1

2 SSP1_RST_N SPI1 reset control 0

0 Resets the SPI1 peripheral.

1 SPI1 reset de-asserted.

3 CAN_RST_N C_CAN reset control 0

0 Resets the C_CAN peripheral.

1 C_CAN reset de-asserted.

31:4 - - Reserved 0x00

Table 8. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit

description

Bit Symbol Value Description Reset

value

Table 9. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description

Bit Symbol Value Description Reset

value

4:0 MSEL Feedback divider value. The division value M is the

programmed MSEL value + 1.

00000: Division ratio M = 1

11111: Division ratio M = 32.

0x000

6:5 PSEL Post divider ratio P. The division ratio is 2 × P. 0x00

0x0 P = 1

0x1 P = 2

0x2 P = 4

0x3 P = 8

31:7 - - Reserved. Do not write ones to reserved bits. 0x0

Table 10. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description

Bit Symbol Value Description Reset

value

0 LOCK PLL lock status 0x0

0 PLL not locked

1 PLL locked

31:1 - - Reserved 0x00

User manual Rev. 3 — 14 January 2011 17 of 413

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Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.5 System oscillator control register

This register configures the frequency range for the system oscillator.

3.5.6 Watchdog oscillator control register

This register configures the watchdog oscillator. The oscillator consists of an analog and a

digital part. The analog part contains the oscillator function and generates an analog clock

(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the

required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can

be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part

Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.

The output clock frequency of the watchdog oscillator can be calculated as

wdt_osc_clk =

Fclkana

(2 × (1 + DIVSEL))

= 7.8 kHz to 1.7 MHz (nominal values).

Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ±40% of the

listed frequency value. The watchdog oscillator is the clock source with the lowest power

consumption. If accurate timing is required, use the IRC or system oscillator.

Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog

oscillator frequency must be programmed by writing to the WDTOSCCTRL register before

using the watchdog oscillator.

Table 11. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit

description

Bit Symbol Value Description Reset

value

0 BYPASS Bypass system oscillator 0x0

0 Oscillator is not bypassed.

1 Bypass enabled. PLL input (sys_osc_clk) is fed

directly from the XTALIN and XTALOUT pins.

1 FREQRANGE Determines frequency range for Low-power

oscillator.

0x0

0 1 - 20 MHz frequency range.

1 15 - 25 MHz frequency range

31:2 - - Reserved 0x00

Table 12. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit

description

Bit Symbol Value Description Reset

value

4:0 DIVSEL Select divider for Fclkana.

wdt_osc_clk = Fclkana/ (2 × (1 + DIVSEL))

00000: 2 × (1 + DIVSEL) = 2

00001: 2 × (1 + DIVSEL) = 4

11111: 2 × (1 + DIVSEL) = 64

8:5 FREQSEL Select watchdog oscillator analog output frequency

(Fclkana).

0x00

0x1 0.5 MHz

0x2 0.8 MHz

User manual Rev. 3 — 14 January 2011 20 of 413

NXP Semiconductors

UM10398

Chapter 3: LPC111x/LPC11Cxx System configuration (SYSCON)

3.5.10 System PLL clock source update enable register

This register updates the clock source of the system PLL with the new input clock after the

SYSPLLCLKSEL register has been written to. In order for the update to take effect, first

write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

3.5.11 Main clock source select register

This register selects the main system clock which can be either any input to the system

PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators

directly. The main system clock clocks the core, the peripherals, and the memories.

The MAINCLKUEN register (see Section 3.5.12

) must be toggled from LOW to HIGH for

the update to take effect.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system

oscillator must be selected.

3.5.12 Main clock source update enable register

This register updates the clock source of the main clock with the new input clock after the

MAINCLKSEL register has been written to. In order for the update to take effect, first write

a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.

Remark: When switching clock sources, both clocks must be running before the clock

source is updated.

Table 16. System PLL clock source update enable register (SYSPLLCLKUEN, address

0x4004 8044) bit description

Bit Symbol Value Description Reset value

0 ENA Enable system PLL clock source update 0x0

0 No change

1 Update clock source

31:1 - - Reserved 0x00

Table 17. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit

description

Bit Symbol Value Description Reset value

1:0 SEL Clock source for main clock 0x00

0x0 IRC oscillator

0x1 Input clock to system PLL

0x2 WDT oscillator

0x3 System PLL clock out

31:2 - - Reserved 0x00

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