28nm CMOS中5G接收机的低噪声放大器设计

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"JSSC_202103 - 一篇关于在28纳米CMOS工艺中设计用于5G接收机的0.02-4.5 GHz低噪声晶体管放大器的文章" 本文详细介绍了在28纳米互补金属氧化物半导体(CMOS)工艺中实现的一种针对5G接收机的新型低噪声放大器（LNA）设计。标题为"404 IEEE Journal of Solid-State Circuits, VOL. 56, NO. 2, FEBRUARY 2021 A0.02–4.5-GHz LNA in 28-nm CMOS for 5G：利用噪声减少和电流复用技术"。该论文发表在电气与电子工程师协会（IEEE）的固体状态电路期刊（JSSC）上，主要关注晶体管级集成电路设计。文章的核心创新在于提出了一种新的噪声降低/消除技术，以提高宽带低噪声跨导放大器（LNTA）的噪声系数（NF）。LNTA由一个用于宽频带输入匹配的共栅（CG）级和一个用于取消CG级噪声和失真的共源（CS）级组成。为了进一步降低噪声，设计中还应用了减少通道热噪声的技术。此外，通过电流复用，即在同一晶体管中重复使用电流，既增加了CS晶体管的跨导，又保持了其较低的功率消耗。实验结果显示，采用28纳米CMOS工艺制造的这种新型LNTA可以驱动外部50欧姆负载，并在1伏单电源供电下，以4.5毫瓦的功率运行。其在20 MHz至4.5 GHz的3-dB带宽范围内实现了2.09-3.2 dB的噪声系数和优于-10 dB的输入回波损耗（S11）。同时，增益（S21）达到15.2 dB，而输入第三阶 intercept 点（IIP3）为-4.6 dBm。这篇论文揭示了如何通过精细的电路设计和创新的噪声管理策略，在有限的功率预算下实现高性能的5G通信接收前端。这种低噪声放大器设计对于提高5G无线通信系统的整体性能，特别是在射频接收链中的噪声抑制和效率方面具有重要意义。通过在28纳米工艺中实现这种高性能LNA，设计者展示了在先进工艺节点上实现高效、低噪声射频组件的可能性，这对于满足5G网络对高数据速率和低延迟的需求至关重要。

270 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 56, NO. 1, JANUARY 2021

Fig. 4. (a) Fundamental auto-zeroing concept [17], [18]. (b) Proposed shared

offset-cancellation method for multiple target ampliﬁers, (c) its ampliﬁer under

calibration, and (d) its auxiliary offset sensing ampliﬁer.

which is signiﬁcantly higher than the inaccuracies caused by

process variations and mismatches of other components. The

variations of resistors by themselves only led to simulated

output variation with σ = 2.69 mV, while the impacts of the

BJT non-idealities introduced output shifts with σ = 2.42 mV.

Several articles report active ampliﬁer offset reduction meth-

ods [9], [10], [16]–[19]. Of particular interest relating to

the approach in this work are auto-zeroing techniques for

operational ampliﬁers [17], [18], as conceptually depicted

in Fig. 4(a). Based on Fig. 4(a), it can be noted that in order

to cancel the offset voltage of the ampliﬁer under calibration

), an auxiliary ampliﬁer (A

) is used. Since A

is not

an ideal ampliﬁer, it has an input-referred offset as well.

When this method is applied, two phases of the clock signal

(5 kHz in this work) ar e utilized. In the ﬁrst clock phase,

the auxiliary ampliﬁer needs to perform an auto-zero action;

then, in the second clock phase, this auxiliar y ampliﬁer is

connected in parallel with the ampliﬁer under calibration to

cancel the input-referred offset voltage of A

. A beneﬁt of

this method is that the ampliﬁer under calibration is operating

continuously, and only the auxiliary ampliﬁer is connected

and disconnected periodically as part of the offset reduction

mechanism.

To avo id the use of one auxiliary ampliﬁer for each ampliﬁer

under offset correction, the modiﬁed method in Fig. 4(b)

utilizes a shared auxiliary ampliﬁer to save die area and

reduce power consumption. Ampliﬁcation stages A

–A

are

part of the ﬁrst ampliﬁer under calibration, while A

–A

are part of the second identical ampliﬁer under calibration.

As shown in Fig. 4(c), the ampliﬁer under calibration is a

folded-cascode topology. I n addition to the main differential

input stage (M

), there is another differential input

pair (M

T11

and M

T12

) to apply the offset-cancellation signal

from the auxiliary ampliﬁer. To intentionally produce an offset

during the characterization testing of this prototype, four

on-chip cascode current sources (I

off_inj

) allow to sink/source

dc current from/to the drains of M

and M

. This current is

mirrored from a tunable reference current. Hence, in the test

mode, the switches SW

or SW

can be closed to generate

an input-referred offset voltage with either polarity to assess

the automatic offset correction scheme. In order to ensure

loop stability for the ampliﬁers under calibration to regulate

both I

CTAT

and I

PTAT

, the output of ampliﬁer A

in Fig. 1 is

loaded by a capacitor C

comp_A1

, as shown in Fig. 4(c), which

creates a dominant pole. The output of ampliﬁer A

in Fig. 1 is

loaded with the series combination of C

comp_A2

and R

comp_A2

in Fig. 4(c), which provides a pole–zero pair. The designs of

the fully differential auxiliary ampliﬁcation stages A

and

are displayed in Fig. 4(d). A

is a transconductance

ampliﬁer used during auto-zeroing to cancel the input-referred

offset introduced by M

and M

. A conventional common-

mode feedback (CMFB) circuit is employed to r egulate the

common-mode output voltage of the fully differential ampli-

ﬁer. Switches S3 and S4 turn o n when the auxiliary ampliﬁer

is in the auto-zero phase, while S1 and S2 turn o n when the

auxiliary ampliﬁer corrects the offset voltage of the a mpliﬁer

under calibration.

With the existence of an auxiliary ampliﬁer, it becom e s

important to ensure the loop’s stability. The loop transfer

function with a single ampliﬁer under calibration has been

derived in [18] as

LoopTF

(

)

o_aux



o_cal



1 +

d_aux





1 +

h_cal





1 +





1 +

d_cal



(9)

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CHEN et al.: 1.16-V 5.8-TO-13.5-ppm/

◦

C CURVATURE-COMPENSATED CMOS BANDGAP RE FERENCE CIRCUIT 271

Fig. 5. Circuit implementation of the multi-sectional temperature-compensated bandgap reference with shared ampliﬁer offset cancellation.



o_cal

≈ g

mT1

·R

cal_o

(10)



o_aux

≈ g

mS1

·R

aux_o

·g

mT11

·R

cal_o

(11)

d_cal

cal_o

·C

cal_load

(12)

cal_o

≈

(

mT8

·r

dsT8

·r

dsT6

)

(

mT10

·r

dsT10

(

dsT4

dsT2

))

(13)

cal_o

≈

(

mS8

·r

dsS8

·r

dsS6

)

(

mS10

·r

dsS10

(

dsS4

dsS2

))

(14)

h_cal

mT5

gsT5

+2C

dbT7

. (15)

In (9)–(15), A

o_aux

is the ope n-loop gain of the auxiliary

ampliﬁer, and A



o_cal

is the gain of the ampliﬁer under cal-

ibration. The terms g

mT8

mT10

mS8

mS10

,andg

mT5

are

the transconductances of transistors M

T10

S10

and M

; whereas r

,andC

represent the drain–source

resistance, gate–source capacitance, and drain-bulk capaci-

tance of the transistors with the corresponding number in

the subscr ipt. C

cal_load

is the outpu t load capacitor of the

ampliﬁer under calibration. For loop stability compensation,

and A

both have a compensation capacitor connected at

the output to form a dominant pole. As an approximation for

each ampliﬁer, it can be assumed that there is a dominant pole

and a high-frequency pole. In (9), ω

d_cal

and ω

h_cal

are the

dominant pole and high-frequency pole of the ampliﬁer under

calibration , while ω

d_aux

is the dominant pole o f the auxiliary

ampliﬁer. The position of the dominant pole is associated with

the output resistance of the folded-cascode ampliﬁer and the

load capacitor in Fig. 4(c), while the ﬁrst high-frequency pole

is located at the drain of M

. By design, pole ω

h_aux

can

be located at much higher frequency, such that it does not

signiﬁcantly affect the stability of the loop. The location of

the zero is designed at ω

= ω

d_cal

· A



o_cal

, which depends

on the dominant pole and the gain of the ampliﬁer under

calibration. This zero forms a doublet with the main ampliﬁer’s

dominant pole, which stabilizes the system. The zero should be

at a lower frequency than the high-frequency pole to improve

the phase margin of the loop, which, in this design, is 70

◦

according to simulations over the complete operational range

(from −40

◦

C to 150

◦

C).

Fig. 5 presents the overall circuit-level implementation of

the bandgap reference. The offset-compensated ampliﬁers A

(i.e., A

–A

) and A

(i.e., A

–A

) are employed within the

current-mode bandgap circuit. The fully differential auxiliary

ampliﬁer (A

–A

) is shared to sense and correct the input-

referred offset voltages of both A

and A

during different

clock cycles. Transistors M

S11

–M

S14

and M

S17

–M

S20

are part

of a CMFB circuit, where the common-mode reference voltage

is connected to the gates of M

S12

and M

S13

. All bias currents

and voltage for the internal ampliﬁers ar e generated within

the chip. Only V

and V

CMFB_ref

are obtained from external

dc voltage sources. The auto-zero reference provides the

common-mode input voltage for the auxiliary ampliﬁer during

the auto-zeroing phase. This reference voltage is designed to

be close to the common-mode input voltage level of ampliﬁers

and A

to reduce glitches during tr ansitions. As visualized

in Fig. 5, three-phase clock signals are generated from a

5-kHz master clock that is obtained from an off-chip signal

generator. This clock is a single-phase signal. Signals φ1–φ3

are g enerated internally from the input master clock signal

using standard digital logic cells. Among these three clock

phases, φ1andφ2 have rising edges that are aligned with the

input clock. Alternatively, φ3 is inverted with respect to the

master clock. All three clock phases are non-overlapping with

each other. Phases φ1andφ2 are for compensation of A

and

respectively, and phase φ3 is used for auto-zeroing the

input differential pair o f A

. The auto-zero voltage signal is

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272 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 56, NO. 1, JANUARY 2021

Fig. 6. (a) Simulated bandgap output v oltages with injected offset currents

to induce positive/negative output deviations before/after the acti vation of

the automatic offset cancellation. (b) Monte Carlo simulation results for the

bandgap output voltage (without the impact of BJT and resistor mismatches).

stored on C

and C

when the circuit is in the ampliﬁcation

mode. To ensure continuous operation of the main ampliﬁers,

the capacitors C

and C

are utilized to store the offset-

cancellation information for both ampliﬁers under calibration

(during their respective phases φ1andφ2) when the circuit

is in the auto-zero phase. The curvature compensation circuit

from Fig. 2 (c) is connected to the output of the b andgap

circuit to provide multi-sectional compensation.

III. E

XPERIMENTAL RESULTS

To evaluate the performance of the offset-cancellation tech-

nique, several current mirrors were included in the main

ampliﬁers of the bandgap reference to inject currents [I

off_inj

in Fig. 4(c)] to purposely generate variable imbalances (i.e.,

ampliﬁer offset voltages) with external control. Since the offset

voltage of an ampliﬁer also has some temperature depen-

dence, the manually introduced offset range should cover the

worst case offset voltage. During the simulations, the injected

offset current emulates the worst case input-referred offset

condition for both ampliﬁers. Furthermore, the active offset

compensation alleviates the temperature dependence due to

its continuous operation in the background.

Fig. 6(a) shows transient simulation results of the bandgap

reference circuit obtained with process corner models for

the devices. Prior to the activation of the offset-cancellation

circuits at 500 μs, the worst case shift of the bandgap

reference output voltage is ±45 mV. After activation of the

Fig. 7. Die photograph of proposed bandgap reference circuit design.

offset-cancellation circuitry, this o utput voltage error reduces

to ±100 μV within 125 μs. Monte Carlo simulations were

completed using foundry-supplied statistical device models

with mismatch and process variations activated. Since the

differential pair is laid out with matching techniques, a cor-

relation coefﬁcient of 0.95 was speciﬁed for the m atched

devices [20]. Fig. 6(b) d isplays the results from 200 Monte

Carlo runs, showing that the estimated bandgap voltage stan-

dard deviation is 0.91 μV with the offset cancellation; here,

in order to evaluate the performance of the active offset-

cancellation circuit, mismatch on the transistors inside both

the ampliﬁer under calibration and the auxiliary ampliﬁer

is enabled. The mismatches among the r esistors and BJTs

were not included in this Monte Carlo simulation since the

circuit cannot reduce the output voltage shift caused by these

non-idealities.

The die photograph is shown in Fig. 7. The chip was

fabricated in a 130-nm technology for power management

applications, which has a permissible supply voltage (V

)

of 3.3V. To pass the design rule checks for this fabrication

process, the “exclude ﬁll” layer was only allowed for a

relatively small portion of the layout, making it difﬁcult to

recognize the lower layers. The active area of the bandgap

reference and auxiliary circuits is 0.08 mm

, including the

area of the bias circuitry (0.015 mm

). T he offset injection

current mirrors occupy 0.05 mm

, which were only added for

characterization testing of this prototype. For testing, the die

was assembled in a DIP-40 package and mounted on an

evaluation printed circuit board. The offset-cancellation circuit

can be activated or de-activated through a control switch.

Figs. 8 and 9 show the bandgap output voltage measure-

ment examples during tests with intentionally created offsets.

Initially, the ampliﬁer imbalances generate bandgap voltage

errors of −46 mV and +31 mV. These shifts are reduced to

below 1 mV after activation of the shared auto-zeroing cir-

cuit. Fig. 10 displays the steady-state bandgap output voltage

measured with automatic offset compensation. The b andgap

output spectra without and with offset cancellation are shown

in Fig. 11. Based on noise simulations, both ampliﬁers under

calibration together have the most dominant noise contribution

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CHEN et al.: 1.16-V 5.8-TO-13.5-ppm/

◦

C CURVATURE-COMPENSATED CMOS BANDGAP RE FERENCE CIRCUIT 273

Fig. 8. Measured bandgap output voltage before and after the acti vation of

the offset cancellation from a test in which a negative input-referred offset

was induced for both ampliﬁers under calibration.

Fig. 9. Measured bandgap output voltage before and after the acti vation of

the offset cancellation from a test in which a positive input-referred offset

was induced for both ampliﬁers under calibration.

Fig. 10. Measured steady-state output voltage after automatic offset

correction.

with approximately 90% of the total noise. Among the noise

sources within these two ampliﬁers, the NMOS transistors

and M

are the major contributors. When the offset

reduction method is activated, the digital switching activity

increases the noise level. Furthermore, note that the auxiliary

offset sensing ampliﬁer (stage s A

and A

) has a simulated

output-referred noise level that is approximately seven times

smaller than that of the ampliﬁers under calibration. Overall,

the measured output noise integrated up to 10 Hz increases

from 84.3 to 175.5 μV, which is the main performance tradeoff

with this active offset compensation. The noise increase might

be too high in some applications, such as for sensor circuits,

but it is tolerable for many power management applications.

First, the switching-mode power supply itself can generate

Fig. 11. Spectrum of the measured bandgap output before (blue) and after

(orange) offset cancellation enabled.

Fig. 12. Measured PSRR of the complete bandgap reference circuit.

signiﬁcant noise, boosting the overall noise ﬂoor, including the

noise at low frequencies [25], [26]. Second, with switching-

mode power supplies, the output voltage ripple can range

from several millivolts to several tens of millivolts. This ripple

voltage is typically dominant compared with the noise of

any internal analog block [27], [28]. For the switched-mode

target application, the bandgap accuracy is signiﬁcantly more

important, as most integrated power management systems

specify the reference voltage accuracy around 1% because this

accuracy directly impacts the regulation accuracy [29], [31].

Fig. 12 displays the power supply rejection ratio (PSRR)

measurement result of the proposed bandgap r eference circuit.

The value at 10 Hz is around -82 dB, and at 1 kHz, the PSRR

is around -63 dB. Due to power supply line ﬁlters for product

chips, the PSRR at higher frequencies is not imperative. The

minimum supply voltage required by the bandgap circuit is

2 V. From 2 to 3.3 V, it can provide a stable output voltage

with a measured line regulation of 0.03%.

Fig. 13 displays the measured output voltages over a tem-

perature range from -40

◦

C to 150

◦

C from seven different chip

samples. Based on the experimental results, the TC varies from

5.8 to 13.5 ppm/

◦

C. The average TC for the seven samples is

8.75 ppm/

◦

C, and the reference voltage mean value at 30

◦

Cis

1.157 V with a stan dard deviation of 6.25 mV. Note that this

standard deviation is likely to increase in the high-volume fab-

rication of product designs due to impacts from package stress,

mechanical stress, and solder stress. The variation is due to

the following main factors. The offset cancellation only c ures

the impact from the offset voltage introduced by the input

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274 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 56, NO. 1, JANUARY 2021

TABLE I

OMPARIS ON WITH OTHER WORKS REGARDING CURVATURE COMPENSATION

Fig. 13. Measured bandgap output voltage versus temperature of seven chips.

differential pair of each ampliﬁer under calibration. Further-

more, the curvature correction circu it alleviates the concave

shape o f the reference voltage over temperature, which has

been optimized over a wide temperature range for the typical

process corner case. From simulations, the transistor process

variations can cause a TC shift between 2.3 and 6.3 ppm/

◦

The polysilico n resistor type used in this d esign has a TC of

around 65 ppm/

◦

C extracted from the simulation of a resistor

over a 125

◦

C temperature range. The resistance increases

with rising temperature. On the contrary, the combined current

PTAT

CTAT

has an opposite temperature trend of approxi-

mately 55 ppm/

◦

C simulated over the same temperature range.

Within the bandgap reference circuit, the partial neutralization

was optimized based on simulations of the typical process

corner case by adjusting the ratios of the transistors that alter

the compensation currents, as described in Section II-A. When

accompanied with resistor process spread, the worst TC can

be in the range of 10.1–13.5 ppm/

◦

C. The circuit without

curvature compensation has a simulated TC of 28.9 ppm/

◦

showing that the curvature compensation circuit improves the

overall TC of the circu it. Fig. 14 reveals an approxim ately

15-mV output voltage range among the untrimmed samples

due to process variations and mismatches between resistors

Fig. 14. Power and area of the main bandgap reference circuit components.

and BJTs, which cannot be compensated by the auxiliary

ampliﬁer. Note that this non-ideality is not compensated

because this design does not include chopping or dynamic

element matching (DEM) techniques. Similar results have

also been reported in previous studies [2], [4]. Generally, this

variation can be reduced further with the use of conventional

trimming techniques for high-volume production.

Fig. 14 shows the power and area breakdown of the designed

bandgap reference circuit components. The auxiliary auto-zero

circuit occupies 15% of the total power consumption and 29%

of the die area. Th e curvature compensation block consumes

14% of the total power and 17% of the chip area. Table I

summarizes the performance measurements of this work in

comparison to other reported results. The proposed untrimmed

circuit exhibits a good TC with a relatively small die size

and measured over a wide temperature range. Compared

with other bandgap reference circuits, the additional power

consumption is due to the offset-cancellation block. However,

even with the inclusion of the power consumption of the input-

referred offset-cancellation circuit, the total power is still in

an acceptable range. This work has a very wide operational

region thanks to the multi-sectional curvature compensation

technique. Compared with the best reported TCs, the overall

performance of this work is similar, especially since other

works without trimming also show worst silicon samples with

around 10 ppm/

◦

C or higher [1], [3]–[5]. These TC ranges

are r ooted in fabrication process variations that naturally

affect the p erformance even when compensation methods are

employed.

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28nm CMOS中5G接收机的低噪声放大器设计

IEEE JSSC 202009: Solid-State Circuits and Integrated Circuits Special Section

2020 IEEE 固态电路会议特刊：高性能通信技术

2021年7月IEEE固态电路期刊：创新设计与应用论文精选

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