"TI SN75DP126 DP转接驱动器产品手册"

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The TI-SN75DP126.pdf is a comprehensive documentation for a DP (DisplayPort) to DP converter driver, designed to facilitate the seamless integration of various display technologies. This innovative product is a valuable tool for professionals in the field of audio-visual technology, offering a reliable and efficient solution for transmitting high-quality digital video and audio signals. The DP converter driver is part of a broader product line that aims to enhance the user experience by enabling connectivity between different devices and display monitors. With its user-friendly interface and advanced features, the driver ensures smooth and uninterrupted transmission of data, regardless of the complexity of the display setup. The product comes with a detailed product folder that provides a wealth of information on its specifications, features, and applications. It also includes technical documents that offer insights into the inner workings of the driver, allowing users to fully understand its capabilities and limitations. Additionally, the product folder contains tools that can assist users in efficiently integrating the driver into their systems. These tools are designed to simplify the installation process and optimize the performance of the converter, ensuring that users can make the most of its capabilities. Overall, the TI-SN75DP126.pdf is a comprehensive resource for professionals in the audio-visual technology industry, offering a powerful and versatile solution for DP conversion and driving. With its advanced features, user-friendly interface, and comprehensive documentation, this product is a valuable asset for anyone looking to enhance their display technology setup.

SN75DP126

www.ti.com.cn

ZHCS794B –FEBRUARY 2012–REVISED AUGUST 2015

7.6 Main Link Input Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

EQ(HBR)

Equalizer gain for RBR/HBR

See Table 4 for EQ setting details;

Max value represents the typical value for the

maximum configurable EQ setting

9 dB

AEQ(HBR2) Equalizer gain for HBR2 18 dB

AEQ(TMDS_D)

Equalizer gain for DP sink in TMDS

mode; data lanes

9 dB

AEQ(TMDS_C)

Equalizer gain for DP sink in TMDS

mode; clock lane

3 dB

AEQ(HDMI_D) EQ gain, HDMI sink; data lanes 9 dB

AEQ(HDMI_C) EQ gain, HDMI sink; clock lane 3 dB

RIN Input termination impedance 40 50 60 Ω

VIterm Input termination voltage AC coupled; self-biased 0 2 V

SQUELCH

Squelch threshold voltage

SQUELCH_SENSITIVITY = 00 60

SQUELCH_SENSITIVITY = 01 (default) 115

SQUELCH_SENSITIVITY = 10 160

SQUELCH_SENSITIVITY = 11 200

7.7 DisplayPort Main Link Output Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OD(L0)

Output Differential Voltage Swing

PRE(L0)

; 675 Mbps D10.2 Test Pattern;

BOOST = 01; 100-Ω R

tdiff

Termination

238 340 442

OD(L1)

357 510 663

OD(L2)

484 690 897

OD(L3)

700 1000 1300

OD(TMDS)

675 Mbps D10.2 Test Pattern; BOOST = 01 420 600 780

ΔV

OD(L0L1)

Output Peak-to-Peak Differential

Voltage Delta

ΔV

ODn

= 20 × log(V

ODL(n+1)

/ V

ODL(n)

)

Per PHY_CTS section 3.2 at TP2

1.7 3.5 5.3

dBΔV

OD(L1L2)

1.6 2.5 3.5

ΔV

OD(L2L3)

0.8 3.5 6.0

PRE(L0)

Driver output pre-emphasis

All V

options; Any BOOST setting 0 0.25

PRE(L1)

= V

OD(L0)

, V

OD(L1)

, or V

OD(L2)

; BOOST = 01 3.5

PRE(L2)

= V

OD(L0)

or V

OD(L1)

; BOOST = 01 6.0

PRE(L3)

= V

OD(L0)

; BOOST = 01 9.5

PRE(BOOST)

Output V

PRE

Boost

BOOST = 10 +15

%dB

BOOST = 00 –15

ΔV

PRE(L1L0)

Pre-emphasis Delta Per PHY_CTS section 3.3 at TP2

2.0

dBΔV

PRE(L2L1)

1.6

ΔV

PRE(L3L2)

1.6

ΔV

ConsBit

Non-transition bit voltage variation Per PHY_CTS section 3.3.5 30 %V

OUT

Driver output impedance 40 50 60 Ω

OCM(SS)

Steady state output common mode

voltage

0 2 V

OCM(PP)

Output common mode noise

Per PHY_CTS section 3.10 RBR, HBR 20

RMS

HBR2 30

Short circuit current limit Main Link outputs shorted to GND 50 mA

SN75DP126

ZHCS794B –FEBRUARY 2012–REVISED AUGUST 2015

www.ti.com.cn

7.8 HDMI/DVI Main Link Output Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Single-end high level output voltage VSadj = 4.7 kΩ V

–10 V

+10 mV

Single-end low level output voltage VSadj = 4.7 kΩ V

–600

–400

SWING

Single-end output voltage swing VSadj = 4.7 kΩ; SDA_CTL/PRE ≤ V

400 600 mV

ΔV

SWING

Change in single-end output voltage swing per 100Ω

ΔVSadj

20 mV

OCM(SS)

Steady state output common mode voltage V

–300 V

-200 mV

ΔV

OCM(SS)

Change in steady state output common mode

voltage between logic levels

–5 5 mV

OD(PP)

Peak-to-peak output differential voltage

VSadj = 4.7 kΩ; SDA_CTL/PRE ≤ V

800 1200

VSadj = 4.7 kΩ; SDA_CTL/PRE ≥ V

640

OD(SS)

Steady state output differential voltage

VSadj = 4.7 kΩ; SDA_CTL/PRE ≤ V

1000

VSadj = 4.7 kΩ; SDA_CTL/PRE ≥ V

630

Short circuit current limit V

= 500 mV 15 mA

7.9 HPD/CAD/EN Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level input voltage

HPD_SNK, CAD_SNK 2.1

EN 0.8

Low-level input voltage

HPD_SNK, CAD_SNK 1.08

EN 0.285

High-level output voltage I

= 500 µA; HPD_SRC, CAD_SRC 2.7 3.6 V

Low-level output voltage I

= 500 µA; HPD_SRC, CAD_SRC 0 0.1 V

outCAD

CAD series output resistance (1) DP_HPD_SNK = CAD_SNK = V

150 Ω

outHPD

HPD series output resistance DP_HPD_SNK = TMDS_HPD_SNK = V

150 Ω

LEAK

Failsafe condition leakage current

= 0 V; V(pin) = 1.2 V; EN 20

μA

= 0 V; V(pin) = 3.3 V; DP_HPD_SNK,

TMDS_HPD_SNK

H_HPD

High level input current

Device powered; V

= 1.9 V;

H_HPD

includes R

pdHPD

resistor current

μA

H_CAD

L_HPD

Low level input current

Device powered; V

= 0.8 V;

IL_HPD includes RpdHPD resistor current

μA

L_CAD

pdHPD

HPD input termination to GND;

DP_HPD_SNK and TMDS_HPD_SNK

= 0 V 100 130 160 kΩ

EN terminal pull-up resistor 120 150 180 kΩ

SN75DP126

www.ti.com.cn

ZHCS794B –FEBRUARY 2012–REVISED AUGUST 2015

7.10 AUX/DDC/I

C Electrical Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I/O capacitance V

= 0 V; f(test) = 1 MHz 10 pF

On resistance AUX_SRCn to

AUX_SNKn in DP mode

= 3.0 V w/ V

= 2.6 V or V

= 3.6 V

w/ V

= 3.4 V; I

= 5 mA

10 Ω

On resistance AUX_SRCp to

AUX_SNKp in DP mode

= 3.0 V w/ V

= 0.3 V or V

= 3.6 V

w/ V

= 0.4 V; I

= 500 mA

10 Ω

On resistance SCL/SDA_SRC to

AUX_SNK in TMDS mode

= 0.4 V; I

= 3 mA 30 Ω

Δr

On resistance variation with input signal

voltage change in DP mode

= 3.6 V, I

= 5 mA, V

= 2.6 V to 3.4 V

= 3.0 V, I

= 5 mA, V

= 0 V to 0.4 V

5 Ω

ID(HYS)

Differential input hysteresis By design (simulation only) 50 mV

LEAK

Failsafe condition leakage current

= 0 V; V(pin) = 3.3 V; SCL/SDA_SNK 40

μA

= 0 V; V(pin) = 3.3 V; AUX_SNK p/n 20

= 0 V; V(pin) = 3.3 V; SCL_CTL/EQ,

SDA_CTL/PRE, AUX_SRCp

= 0 V; V(pin) = 3.3 V; AUX_SRCn,

SCL/SDA_SRC

H_AUX_DD

AUX/DDC High level input current

Device powered; V

= V

μA

H_I2C

C High level input current 20

L_AUX

AUX Low level input current

Device powered; V

= GND ;

L_DDCSRC

includes R

DDC

resistor current

μA

L_I2C

C Low level input current 40

L_DDCSR

DDC Low level input current 80

AUX+

AUX_SNKp voltage Per PHY_CTS section 3.19 0 0.4 V

AUX–

AUX_SNKn voltage Per PHY_CTS section 3.18 2.4 3.6 V

1122

AC coupled AUX line insertion loss V

= 400 mV, 360 MHz sine wave 3 dB

DDC

Switchable pullup resistor on DDC at

source side (SCL_DDC, SDA_DDC)

CAD_SNK = V

48 60 72 kΩ

IL1

SCL/SDA_SRC low-level input voltage

OVS ≥ V

0.4

IL2

OVS at V

0.4

IL3

OVS ≤ V

0.3

OL1

SCL/SDA_SRC low-level output voltage

OVS ≥ V

0.6 0.7

OL2

OVS at V

0.5 0.6

OL3

OVS ≤ V

0.4 0.5

OL4

SCL/SDA_SNK and SCL/SDA_CTL low-

level output voltage

= 3 mA 0.4 V

7.11 DisplayPort Main Link Output Switching Characteristics

over recommended operating conditions (unless otherwise noted) Figure 1 and Figure 2

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Propagation delay time 350 ps

SK1

Intra-pair output skew

Signal input skew = 0 ps; dR = 2.7 Gbps, V

PRE

= 0 dB,

800 mVpp , D10.2 clock pattern at device input; see Figure 2

20 ps

SK2

Inter-pair output skew 70 ps

Δt

jit

Total peak to peak residual

jitter

(L0); VPRE(L0); EQ = 8 dB; clean source; minimum input and

output cabling; 1.62 Gbps, 2.7 Gbps, and 5.4-Gbps PRBS7 data

pattern.

15 ps

sq_enter

Squelch Entry Time

Time from active DP signal turned off to ML output off with noise

floor minimized

10 120 μs

sq_exit

Squelch Exit Time Time from DP signal on to ML output on 0 1 μs

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