SN75DP130
ZHCS202E –APRIL 2011–REVISED MARCH 2015
www.ti.com.cn
Electrical Characteristics (接接下下页页)
over recommended operating conditions (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS MIN TYP MAX UNIT
Change in steady state
output common-mode
ΔV
OCM(SS)
Tested in compliance to section 3.10 in CTS 1.1a 10 mV
PP
voltage between logic
levels
20
Output common-mode
V
OCM(PP)
HBR2 mV
RMS
noise
30
V
SQUELCH
Squelch threshold voltage Programable through I
2
C; default at 80 mVpp typical 80 mV
PP
I
TXSHORT
Short circuit current limit Main Link outputs shorted to GND 50 mA
HPD_SRC, CAD_SRC
V
OH
High-level output voltage I
OH
= 500 µA 2.7 3.6 V
V
OL
Low-level output voltage I
OH
= 500 µA 0 0.1 V
CAD series output
R
outCAD
EN = RSTN = V
CC
; HPD_SNK = CAD_SNK = V
CC
150 Ω
resistance
(2)
HPD series output
R
outHPD
EN = RSTN = V
CC
; HPD_SNK = CAD_SNK = V
CC
150 Ω
resistance
V
CC
= 0 V, V(pin) = 1.2 V; RSTN 20
V
CC
= 0 V, V(pin) = 3.3 V; SCL/SDA_CTL, AUX_SNKp/n 20
I
LEAK
Leakage current
(3)
μA
V
CC
= 0 V, V(pin) = 3.3 V; HPD_SNK 40
V
CC
= 0 V, V(pin) = 3.3 V; AUX_SRCp/n 60
HPD_SNK
V
IH
= 1.9 V (leakage includes the 130-kΩ pull-down
I
H
High-level input current –30 30 µA
resistor)
V
IL
= 0.8 V (leakage includes the 130-kΩ pull-down
I
L
Low-level input current –30 30 µA
resistor)
Positive going input
V
TH+
1.4 V
threshold voltage
HPD input termination to
R
pdHPD
V
CC
= 0 V 100 130 160 kΩ
GND
CAD_SNK
I
H
High-level input current V
IH
= 1.9 V –1 1 µA
I
L
Low-level input current V
IL
= 0.8 V –1 1 µA
Positive going input
V
TH+
1.4 V
threshold voltage
AUX/DDC/I
2
C
DDC mode passthrough
V
PASS
V
CAD_SNK
= V
IH
; I
O
= 100 µA 1.9 V
voltage
C
IO
I/O capacitance V
IO
= 0 V; f(test) = 1 MHz 10 pF
On resistance AUX_SRCn V
CC
= 3 V w/ V
I
= 2.85 V or
5 10
to AUX_SNKn in DP mode V
CC
= 3.6 V w/ V
I
= 3.4 V; I
O
= 5 mA
On resistance
r
ON
SCL/SDA_DDC to I
O
= 3 mA 15 30 Ω
AUX_SNK in TMDS mode
On resistance AUX_SRC to
I
O
= 3 mA 10 20
AUX_SNK in TMDS mode
On resistance variation with
V
CC
= 3.6 V, I
O
= 5 mA, V
I
= 2.6 to 3.4 V,
Δr
ON
input signal voltage change 5 Ω
V
CC
= 3 V, I
O
= 5 mA, V
I
= 0 to 0.4 V
in DP mode
V
ID(HYS)
Differential input hysterisis By design (simulation only) 50 mV
I
H
High-level input current V
I
= V
CC
–5 5 µA
(2) A series output resistance of 100kΩ may be added in series to the CAD_SRC output to mimic a cable adapter.
(3) Applies to failsafe inputs: RSTN, SDA_CTL, SCL_CTL, SDA_DDC, SCL_DDC, AUX_SNK P/N, AUX_SRC P/N, HPD_SNK
10 版权 © 2011–2015, Texas Instruments Incorporated
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