"TI-SN75DP130.pdf: DP转接驱动器产品样本"

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The TI-SN75DP130.pdf is a document that provides detailed information about the DP (DisplayPort) transceiver driver. The DP transceiver driver is a crucial component in electronic devices that require high-speed data transmission, such as laptops, desktop computers, and monitors. The document outlines the features and specifications of the DP transceiver driver, including its operating voltage, data rate, and power consumption. It also includes a detailed block diagram of the driver, illustrating how it interfaces with other components in a typical DP system. One of the key features of the DP transceiver driver is its ability to support high-speed data transmission rates, which are necessary for modern display technologies such as 4K and 8K resolution. The driver is also designed to be compatible with the latest DP standards, ensuring seamless integration with other DP-compliant devices. In addition to its technical specifications, the document also provides information on how to use and configure the DP transceiver driver in various applications. This includes guidelines on how to connect the driver to other components, as well as recommendations for optimizing its performance. Overall, the TI-SN75DP130.pdf is a comprehensive resource for engineers and designers working on DP-enabled devices. By providing detailed information on the DP transceiver driver and how to use it effectively, the document helps ensure the successful implementation of DP technology in a wide range of electronic products.

SN75DP130

ZHCS202E –APRIL 2011–REVISED MARCH 2015

www.ti.com.cn

Electrical Characteristics (接接下下页页)

over recommended operating conditions (unless otherwise noted)

PARAMETER

(1)

TEST CONDITIONS MIN TYP MAX UNIT

Change in steady state

output common-mode

ΔV

OCM(SS)

Tested in compliance to section 3.10 in CTS 1.1a 10 mV

voltage between logic

levels

Output common-mode

OCM(PP)

HBR2 mV

RMS

noise

SQUELCH

Squelch threshold voltage Programable through I

C; default at 80 mVpp typical 80 mV

TXSHORT

Short circuit current limit Main Link outputs shorted to GND 50 mA

HPD_SRC, CAD_SRC

High-level output voltage I

= 500 µA 2.7 3.6 V

Low-level output voltage I

= 500 µA 0 0.1 V

CAD series output

outCAD

EN = RSTN = V

; HPD_SNK = CAD_SNK = V

150 Ω

resistance

(2)

HPD series output

outHPD

EN = RSTN = V

; HPD_SNK = CAD_SNK = V

150 Ω

resistance

= 0 V, V(pin) = 1.2 V; RSTN 20

= 0 V, V(pin) = 3.3 V; SCL/SDA_CTL, AUX_SNKp/n 20

LEAK

Leakage current

(3)

μA

= 0 V, V(pin) = 3.3 V; HPD_SNK 40

= 0 V, V(pin) = 3.3 V; AUX_SRCp/n 60

HPD_SNK

= 1.9 V (leakage includes the 130-kΩ pull-down

High-level input current –30 30 µA

resistor)

= 0.8 V (leakage includes the 130-kΩ pull-down

Low-level input current –30 30 µA

resistor)

Positive going input

TH+

1.4 V

threshold voltage

HPD input termination to

pdHPD

= 0 V 100 130 160 kΩ

GND

CAD_SNK

High-level input current V

= 1.9 V –1 1 µA

Low-level input current V

= 0.8 V –1 1 µA

Positive going input

TH+

1.4 V

threshold voltage

AUX/DDC/I

DDC mode passthrough

PASS

CAD_SNK

= V

; I

= 100 µA 1.9 V

voltage

I/O capacitance V

= 0 V; f(test) = 1 MHz 10 pF

On resistance AUX_SRCn V

= 3 V w/ V

= 2.85 V or

5 10

to AUX_SNKn in DP mode V

= 3.6 V w/ V

= 3.4 V; I

= 5 mA

On resistance

SCL/SDA_DDC to I

= 3 mA 15 30 Ω

AUX_SNK in TMDS mode

On resistance AUX_SRC to

= 3 mA 10 20

AUX_SNK in TMDS mode

On resistance variation with

= 3.6 V, I

= 5 mA, V

= 2.6 to 3.4 V,

Δr

input signal voltage change 5 Ω

= 3 V, I

= 5 mA, V

= 0 to 0.4 V

in DP mode

ID(HYS)

Differential input hysterisis By design (simulation only) 50 mV

High-level input current V

= V

–5 5 µA

(2) A series output resistance of 100kΩ may be added in series to the CAD_SRC output to mimic a cable adapter.

(3) Applies to failsafe inputs: RSTN, SDA_CTL, SCL_CTL, SDA_DDC, SCL_DDC, AUX_SNK P/N, AUX_SRC P/N, HPD_SNK

SN75DP130

www.ti.com.cn

ZHCS202E –APRIL 2011–REVISED MARCH 2015

Electrical Characteristics (接接下下页页)

over recommended operating conditions (unless otherwise noted)

PARAMETER

(1)

TEST CONDITIONS MIN TYP MAX UNIT

= GND; CAD_SNK = V

–5 5

Low-level input current µA

= GND; At DDC inputs 80

Voltage on the Aux+ for 1M (5%) pullup to V

and 100-kΩ pulldown to GND on

AUX+

0 0.4 V

PHY-CTS 3.19 AUX+; V

= 3.3 V

100 kΩ pullup to V

and 1M (5%) pulldown to GND on

Voltage on the Aux- for

AUX-

AUX-; 2.4 3.6 V

PHY-CTS 3.18

= 3.3 V

Differential line insertion V

= 400 mV, AC coupled; p-channel biasing 0.3 V and

1122

| 1.6 3 dB

loss N-channel 3 V; 360-MHz sine wave; CAD_SNK = V

Switcheable pul-lup resistor

DDC

on DDC at source side CAD_SNK = V

48 60 72 kΩ

(SCL_DDC, SDA_DDC)

7.7 Switching Characteristics

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

MAIN LINK

Propagation delay time See 图 10 300 ps

SK(1)

Intra-pair output skew 20 ps

Signal input skew = 0ps; d

= 2.7 Gbps, V

PRE

= 0 dB, 800

mVp-p, D10.2 clock pattern at device input; See 图 11

SK(2)

Inter-pair output skew 100 ps

OD(L0)

; V

PRE(L0)

; EQ = 8 dB; clean source; minimum input

Δt

jit

Total peak-to-peak residual jitter and output cabling; 1.62 Gbps, 2.7 Gbps, and 5.4 Gbps 15 ps

PRBS7 data pattern.

Time from active DP signal turned off to ML output off with

sq_enter

Squelch entry time 10 120 μs

noise floor minimized

sq_exit

Squelch exit time Time from DP signal on to ML output on 0 1 μs

HPD/CAD

Propagation delay HPD_SNK to

PD(HPD)

50 ns

HPD_SRC

= 3 V; See 图 1

Propagation delay CAD_SNK to

PD(CAD)

50 ns

CAD_SRC

T(HPD)

HPD logic shut off time V

= 3 V; See 图 2 400 ms

AUX/DDC/I

= 400 mV, AC coupled; p-channel biasing 0.3V and

sk(AUX)

Intra-pair skew 400 ps

N-channel 3 V; See 图 13

Propagation delay time, low to

PLH(DP)

3 ns

high

CAD = V

; 1-Mbps pattern;See 图 14

Propagation delay time, high to

PHL(DP)

3 ns

low

Propagation delay time, low to

PLH(DDC)

50 ns

high

CAD = V

; 100-kbps pattern

Propagation delay time, high to

PHL(DDC)

50 ns

low

= 0.1 V, V

ICMM

= 2-V source side (before AC coupling

PU(AUX)

Main Link D3 wake-up time 50 µs

caps)

Refer to the I

C-Bus Specification, Version 2.1 (January 2000); SN75DP130 meets the switching characteristics for standard mode

transfers up to 100 kbps.

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