Intel IXP2400: 高性能网络处理器技术规格

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"Intel IXP2400 网络处理器数据手册" Intel IXP2400 网络处理器是一款专为智能网络服务快速部署设计的高性能处理芯片。这款处理器提供了高度的编程灵活性、代码重用以及高效处理能力，能够支持各种广域网（WAN）和局域网（LAN）应用，覆盖了从OC-3到OC-48的广泛速度范围。其核心特性在于创新的微引擎架构，该架构实现了高性能和可扩展性。 1. **微引擎架构**：IXP2400的核心是八颗集成的微引擎版本2处理器。这些微引擎运行频率可达400MHz或600MHz，通过多线程分布缓存架构实现了软件中的流水线特性，提升了在高速网络环境下的处理效率。 2. **多线程通信**：微引擎具有创新的线程间通信功能，能够在高线路速率下实现高效的处理，确保在网络流量高峰期也能保持稳定性能。 3. **通用硬件元素**：处理器内置通用硬件元件，支持高级网络算法，增强了对复杂网络操作的支持，适应不断演进的网络需求。 4. **Intel® Exchange Architecture (IXA)**：IXP2400处理器是Intel IXA存储转发架构的关键组成部分。IXA架构为融合通信环境提供了灵活且功能丰富的网络处理，能够在语音、数据和视频等多业务环境中有效工作。 5. **配置灵活性**：处理器可以配置为不同的工作模式，以适应不同应用场景，这包括但不限于协议处理、流量管理、服务质量（QoS）控制、安全过滤等。 6. **性能与可扩展性**：IXP2400通过其架构设计实现了高吞吐量和低延迟，使得系统能够随着网络需求的增长而平滑扩展，确保了服务质量和网络稳定性。 7. **网络应用支持**：IXP2400适用于多种网络设备，如路由器、交换机、边缘服务器等，能够为VoIP、视频流、宽带接入等高带宽服务提供强大支撑。 Intel IXP2400网络处理器通过其先进的微引擎设计和强大的硬件特性，为网络设备制造商提供了构建高效、灵活和可扩展网络解决方案的基石，从而满足了现代网络环境中不断增长的带宽需求和服务智能化趋势。

Intel

IXP2400 Network Processor

16 Datasheet

Context and a working copy of each. When a Context goes to Sleep state, the value of the working

copies is put into the Context’s copy of LM_Addr. When the Context returns to the Executing state,

the value in its copy of LM_Addr are put into the working copies. The choice of LM_Addr_0 or

LM_Addr_1 is selected in the instruction.

2.3.6 CRC Unit

The CRC Unit operates in parallel with the Execution Datapath. It takes two operands, performs a

CRC operation, and writes back a result. CRC-16 and CRC-32 are supported. One of the operands

is the CRC_Remainder Local CSR, and the other is a GPR, Transfer In Register, Next Neighbor, or

LM, specified in the instruction and passed through the Execution Datapath to the CRC Unit. The

instruction specifies the CRC operation type.

2.3.7 Event Signals

Event Signals are used to coordinate a program with completion of external events. For example,

when a ME issues a command to an external unit to read data (which will be written into a

Transfer_In register), the program must ensure that it does not try to use the data until the external

unit has written it. There is no hardware mechanism to flag that a register write is pending, and then

prevent the program from using it. Instead the coordination is under software control, with

hardware support.

When the program issues the command to the external event, it can request that the external unit

supply an indication (called an Event Signal) that the command has been completed. There are 15

Event Signals per Context that can be used, and Local CSRs per Context to track which Event

Signals are pending and which have been returned. The Event Signals can be used to move a

Context from Sleep state to Ready state, or alternatively, the program can test and branch on the

status of Event Signals. Event Signals can be set in nine different ways:

1. When data is written into S_Transfer_In Registers (part of S_Push_ID input)

2. When data is written into D_Transfer_In Registers (part of D_Push_ID input)

3. When data is taken from S_Transfer_Out Registers (part of S_Pull_ID input)

4. When data is taken from D_Transfer_Out Registers (part of D_Pull_ID input)

5. On InterThread_Sig_In input

6. On NN_Sig_In input

7. On Prev_Sig_In input

8. On write to Same_ME_Signal Local CSR

9. By Internal Timer

2.4 DDR SDRAM

The DDR Memory Controller controls the off-chip DRAM. The DDR Controller contains the

mechanism that allows the other functional units to access the single channel of DRAM present in

the IXP2400. DRAM sizes of 64 MB, 128 MB, 512 MB and 1 GB are supported. Single-sided or

double-sided DIMMs are supported. The IXP2400 only supports 4-bank DDR devices. Table 1

shows the supported configurations. The addressing capability of the DDR Controller is 2 GB. The

address space always appears contiguous to software executing on the IXP2400. If less than 2 GB

Intel

IXP2400 Network Processor

Datasheet 17

of physical memory is present, the upper part of the address space is not utilized. Read and writes

to DRAM generated by the MEs, the Intel XScale core, and PCI units, are presented as requests to

the DDR controller, which enqueues them to their respective bank(s).

Error Correction Code (ECC) is supported. Each 64 bits (8 bytes) has an 8-bit ECC associated with

it, thus all single bit errors are corrected while multiple bit errors are detected and optionally

reported. The ECC operation can be disabled. When ECC is enabled, partial writes (writes of less

than 8 bytes) will be performed as read-modify-write by the DDR controller.

2.5 SRAM

The IXP2400 has two independent SRAM controllers, each of which supports pipelined QDR

synchronous static RAM (SRAM) and/or a coprocessor that adheres to QDR signaling. Either

controller can be left unused if the application does not need to use its SRAM channels, which are

accessible by the Microengines, the Intel XScale core, and the PCI Unit (external bus masters).

The memory is logically four bytes (32 bits) wide; physically the data pins are two bytes wide and

are double clocked. Byte parity is supported. Each of the four bytes has a parity bit, which is

generated when the byte is written and checked when the data is read. There are byte enables that

select which bytes to write for writes of less than 32 bits.

Examples of supported SRAMs are:

Table 1. DDR Supported Configurations

Memory

Capacity

DRAM

Density

Part

Width

Total

Number of

SDRAMs

Number

of DIMMs

Number

Sides

Comments (sample

DIMM vendors shown)

64 MB

64 Mbit x8 9 1 1

128 Mbit x16 5 1 1

128 MB

64 Mbit x8 18 1 2

128 Mbit x8 9 1 1 Samsung*, Micron*

128 Mbit x16 10 1 2

256 Mbit x16 5 1 1

256 MB

128 Mbit x8 18 1 2 Samsung*, Micron*

256 Mbit x16 10 1 2 Samsung*

256 Mbit x16 10 1 2

512 Mbit x16 5 1 1

512 MB

256 Mbit x8 18 1 2 Samsung*, Micron*

512 Mbit x8 9 1 1

512 Mbit x16 10 1 2

1.0 Gbit x16 5 1 1

1.0 GB

512 Mbit x 8 18 1 2

1.0 Gbit x 8 9 1 1

1.0 Gbit x16 10 1 2

2.0 GB 1.0 Gbit x8 18 1 2

Intel

IXP2400 Network Processor

20 Datasheet

• A Flow Control Interface, which provides a point-to-point connection used to pass CSIX-L1-B

flow control C-Frames either between two IXP2400 network processors or between a IXP2400

and a CSIX-L1-B switch fabric.

• Each 32-bit interface can be subdivided into 8- or 16-bit channel combinations. The MSF

interface uses 3.3V LVTTL (low-voltage transistor-transistor logic) signaling. While the

CSIX standard is a source-synchronous bus, the IXP2400 uses a common-clocking scheme for

compatibility with the other protocols.

In UTOPIA and POS-PHY modes, each port can function as a single 32-bit interface, or can be

subdivided into a combination of 8- or 16-bit channels. Each channel is a point-to-point connection

to a single physical layer device. Each Channel operates independently when subdivided. In

addition to single-PHY mode, the IXP2400 supports multi-PHY (MPHY) mode. In MPHY mode,

the 32-bit bus is shared by up to 16 ports in accordance with the UTOPIA Level 3 and POS PHY

Level 3 Specifications. Master Mode only is supported in UTOPIA and POS-PHY modes.

Note: SPI3 is the name associated with POS-PHY Level 3.

The Optical Inter-networking Forum (OIF) controls the SPI3 Implementation Agreement

document (available at http://www.oiforum.com).

2.6.2 CSIX

The IXP2400 implements CSIX_L1 (Common Switch Interface) for signalling and clocks.

CSIX_L1 defines an interface between a Traffic Manager (TM) and a Switch Fabric (SF) for ATM,

IP, MPLS, Ethernet, and similar data communications applications. The basic unit of information

transferred between TMs and SFs is called a CFrame. There are a number of CFrame types defined,

but they can be basically categorized as either Data, Control, or Flow Control. Associated with

each CFrame is information such as length, type, address. This information is collected by the MSF

and passed to Microengines.

The Network Processor Forum (NPF) controls the CSIX_L1 specification (available at

http://www.npforum.org).

2.7 PCI Controller

The PCI Controller provides 64-bit, 66-MHz-capable PCI Rev. 2.2 interface. It is also compatible

to 32-bit and/or 33-MHz PCI devices. The PCI controller provides the following functions:

• Target access (external bus master access to SRAM, DRAM, and CSRs)

• Master access (Intel XScale core or Microengine access to PCI target devices)

• Three DMA channels

• Mailbox and Doorbell Registers for Intel XScale core-to-host communication

• PCI arbiter

The IXP2400 can be configured to act as PCI central function, or can own the arbitration.

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Intel IXP2400: 高性能网络处理器技术规格

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