TI TPS6593-Q1：汽车应用的低功耗5 buck和4 LDO电源管理IC

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TI-TPS6593-Q1是一款专为汽车应用设计的高性能电源管理集成电路（PMIC）。该产品在满足严苛的汽车行业标准的同时，提供了低功耗和高效的电力转换解决方案。首先，TPS6593-Q1经过了严格的汽车应用认证(Automotive Applications)，符合AEC-Q100规范，这意味着它能在宽广的工作电压范围内（3V至5.5V）稳定运行，适应低温环境（-40°C）至高温条件（+125°C），确保了在各种严酷条件下都能保持可靠性和稳定性。它还达到了HBM等级2和CDM等级C4A，显示出其在电磁兼容性和电流跌落保护方面的优异性能。在节能方面，这款PMIC具有极低的待机模式电流，典型值仅为2μA在关断模式下，备份供电仅模式下为7μA，而在低功耗standby模式下仅为20μA，显著降低了对电池续航的影响。 TPS6593-Q1集成了五个开关稳压器（BUCK）模块，提供灵活多阶段电源转换能力。其中有一个支持高达4A的输出，另外三个可达到3.5A，还有一个具备2A输出。这些模块支持输出电压范围广泛，从0.3V到3.34V，以5、10或20mV的步进调节，使得系统设计师能够根据需求定制精确的电压级。此外，它还内置短路保护和过流保护功能，以及软启动机制，防止设备启动时电流过大。特别值得注意的是，这款IC的四个BUCK模块具备多相能力，可以从单个电源轨源出高达14A的电流，这大大提高了电源效率和灵活性。同时，它支持与外部时钟同步，便于集成到多种系统架构中。另外，TPS6593-Q1还配备了三个低降压线性稳压器（LDO），具有可配置的旁路模式，输出电压范围为0.6V至3.3V，步进50mV，每个LDO可以提供高达500mA的电流，为系统中的低电压负载提供稳定的支持。 TI-TPS6593-Q1凭借其高度集成、高效率和多功能特性，成为汽车电子应用的理想选择，尤其适合那些对电源管理有严格要求的领域，如车载信息娱乐系统、汽车照明和电池管理系统等。它的设计精良和可靠性使其在汽车行业中树立了新的性能标杆。

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7.1 Absolute Maximum Ratings (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the thermal/ground pad of the

device.

(1)

POS MIN MAX UNIT

M4 Storage temperature, T

stg

–65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at conditions beyond those indicated under Recommended Operating

Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) The voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8

V. VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature.

7.2 ESD Ratings

POS VALUE UNIT

M5 V

(ESD)

Electrostatic

discharge

Human-body model (HBM), per AEC Q100-002

(1)

±2000 V

M6 V

(ESD)

Electrostatic

discharge

Charged-device model (CDM), per AEC Q100-011 ±500 V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the thermal/ground pad of the

device.

POS MIN NOM MAX UNIT

R1.3 Voltage on OV protected supply input pin VCCA

VCCA_U

5.5 V

R1.4 Voltage on all buck supply input pins PVIN_Bx 2.6 3.8 5.5 V

R1.4a

Voltage difference between supply input

pins

Between VCCA and each PVIN_Bx –0.2 0.2 V

R1.5 Voltage on all buck switch nodes SW_Bx pins 3.3 5.5 V

R1.6

Voltage on all buck voltage sense

nodes

(1)

FB_Bx 0 V

OUT_Bn,max

R1.7a

Voltage on all LDO supply voltage input

pins

PVIN_LDO12, PVIN_LDO3 1.2 3.3 VCCA V

R1.7b PVIN_LDO4 2.2 3.3 VCCA V

R1.8 Voltage on all LDO output pins

(1)

VOUT_LDOx 0 3.3 V

R1.9 Voltage on internal LDO output pins VOUT_LDOVINT, VOUT_LDOVRTC 1.65 1.95 V

R1.10 Voltage on reference ground pins REFGNDx –0.3 0.3 V

R1.11

Voltage on I/O supply pin

VIO_IN

= 1.8 V 1.7 1.8 1.9

R1.12 V

VIO_IN

= 3.3 V 3.135 3.3

VCCA, up to

3.465V

R1.13

Voltage on logic pins (input or output) in

VIO domain

C and SPI pins, nRSTOUT &

nRSTOUT_SoC pins, GPIO1, GPIO2,

GPIO7, GPIO8, GPIO9, GPIO10, and

GPIO11 pins

0 V

VIO_IN

VIO_IN,max

R1.14 Voltage on backup supply pin VBACKUP 0

Full Battery,

up to 5.5V

R1.15 Voltage on crystal oscillator pins OSC32KIN, OSC32KOUT, OSC32KCAP 0

OUT_LDOVRT

C,max

R1.16

Voltage on logic pins (input or output) in

LDOVRTC domain

With fail-safe

(3)

: GPIO3 & GPIO4 0 1.8

OUT_LDOVRT

C,max

R1.17

Voltage on logic pins (input or output) in

LDOVINT domain

With fail-safe

(3)

: GPIO5 to GPIO6 0 1.8

OUT_LDOVIN

T,max

TPS6593-Q1

SLVSE83 – DECEMBER 2020

www.ti.com

ADVANCE INFORMATION

16 Submit Document Feedback

Product Folder Links: TPS6593-Q1

7.5 General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the thermal/ground pad of the

device.

POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Electrical Characteristics

1.1a C

IN(LDOn)

Input filtering

capacitance

(1)

Connected from PVIN_LDOn to GND, Shared

input tank capacitance (depending on platform

requirements)

1 2.2 µF

1.1b C

OUT(LDOn)

Output filtering effective

capacitance

(2)

Connected from VOUT_LDOn to GND 1 2.2 4 µF

1.1c

ESR

(LDOn)

Filtering capacitor ESR

(3)

1 MHz ≤ f ≤ 10 MHz 20 mΩ

1.1d

OUT_TOTAL

(

LDOn)

Total capacitance at output

(Local + POL)

(5)

1 MHz ≤ f ≤ 10 MHz 20 µF

1.2a V

IN(LDOn)

LDO Input voltage LDO mode 1.2 VCCA V

1.2b

IN(LDOn)_byp

ass

LDO Input voltage in

bypass mode

Bypass mode 1.7

VCCA,

upto 3.6

1.3 V

OUT(LDOn)

LDO output voltage

configurable range

LDO mode, with 50-mV steps 0.6 3.3 V

1.4a

DCOV(LDOn)

Total DC output voltage

accuracy, including voltage

references, DC load and

line regulations, process

and temperation variations

LDO mode, V

IN(LDOn)

- V

OUT(LDOn)

> 300 mV,

OUT(LDOn)

≥ 1V

–1% 1%

1.4b

LDO mode, V

IN(LDOn)

- V

OUT(LDOn)

> 300 mV,

OUT(LDOn)

< 1V

–10 10 mV

1.6 I

OUT(LDOn)

Output current V

IN(LDOn)min

≤ V

IN(LDOn)

≤ V

IN(LDOn)max

500 mA

1.7 I

SHORT(LDOn)

LDO current limitation LDO mode and bypass mode 750 1500 mA

1.8a

IN_RUSH(LDOn

)

LDO inrush current

LDOn_BYPASS = 0 1500

LDOx_BYPASS = 1, with maximum 50-µF load

connected to VOUT_LDOn

1500

1.11a R

DIS(LDOn)

Pulldown discharge

resistance at LDO output

Active only when converter is disabled. Also

applies to bypass mode. LDOn_PLDN = '00'

35 50 65 kΩ

1.11b R

DIS(LDOn)

Pulldown discharge

resistance at LDO output

Active only when converter is disabled. Also

applies to bypass mode. LDOn_PLDN = '01'

60 125 200 Ω

1.11c R

DIS(LDOn)

Pulldown discharge

resistance at LDO output

Active only when converter is disabled. Also

applies to bypass mode. LDOn_PLDN = '10'

120 250 400 Ω

1.11d R

DIS(LDOn)

Pulldown discharge

resistance at LDO output

Active only when converter is disabled. Also

applies to bypass mode. LDOn_PLDN = '11'

240 500 800 Ω

1.12a

PSRR

VIN(LD

On)

Power supply ripple

rejection from V

IN(LDOn)

f = 1 kHz, V

IN(LDOx)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

500 mA

1.12b

f = 10 kHz, V

IN(LDOx)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

= 500 mA

1.12c

f = 100 kHz, V

IN(LDOx)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

= 500 mA

1.12d

f = 1 MHz, V

IN(LDOx)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

500 mA

1.13 I

Qoff(LDOn)

Quiescent current, off

mode

For LDO1, LDO2, & LDO3, VCCA = V

IN(LDOn)

3.3 V, T

= 25°C

2 µA

1.14a

Qon(LDOn)

Quiescent current, on

mode

LDOn_BYPASS = 0, I

LOAD

= 0 mA , T

= 25°C 70

µA

1.14b LDOn_BYPASS = 1, I

LOAD

= 0 mA , T

= 25°C 60

1.15 T

LDR(LDOn)

Transient load regulation,

ΔV

OUT

(4)

LDOn_BYPASS = 0, I

OUT

= 20% to 80% of

OUTmax

, t

= t

= 1 µs

25 mV

1.16

BYPASS_to_L

DO(LDOn)

Transient regulation due to

Bypass Mode to Linear

Mode Transition

IN(LDOn)

= 3.3V, I

OUT

OUT(LDOn)max

LDOn_BYPASS bit switches between 1 and 0

-2 mV

TPS6593-Q1

SLVSE83 – DECEMBER 2020

www.ti.com

ADVANCE INFORMATION

18 Submit Document Feedback

Product Folder Links: TPS6593-Q1

7.5 General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level refers to the thermal/ground pad of the

device.

POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

1.17 V

NOISE(LDOn)

RMS Noise

100 Hz < f ≤ 100 kHz, V

= 3.3 V, V

OUT

= 1.8 V,

OUT

= 300 mA

250 µV

RMS

1.18 Ripple From the internal charge pump 5 mV

1.19a

BYPASS(LDO

Bypass resistance

3.1 V ≤ V

IN(LDOn)

≤ 3.5 V, PVIN_LDOx ≤ VCCA,

OUT

= 500 mA, LDOx_BYPASS = 1

200

mΩ

1.19c

1.7 V ≤ V

IN(LDOn)

≤ 1.9 V, I

OUT

= 500 mA,

LDOn_BYPASS = 1

250

1.20

TH_SC_RV(LD

On)

Threshold voltage for Short

Circuit and Residual

Voltage Detection

LDOx_EN = 0 140 150 160 mV

Timing Requirements

19.1 t

on(LDOn)

Turnon time

Time between enable of the LDOn to within

OV/UV monitor level

500 µs

19.2a

ramp(LDOn)

Ramp up slew rate

VOUT from 0.3 V to 90% of LDOn_VSET.

LDOn_SLOW_RAMP = 0

25 mV/µs

19.2b

VOUT from 0.3 V to 90% of LDOn_VSET.

LDOn_SLOW_RAMP = 1

3 mV/µs

19.3a

delay_OC(LDO

Over-current detection

delay

Detection singal delay when I

OUT

> ILIM 35 µs

19.3b

deglitch_OC(LD

On)

Over-current detection

signal deglitch time

Digital deglitch time for the over-current

detection signal

38 44 µs

19.4

latency_OC(LD

On)

Over-current signal total

latency time

Total delay from I

out

> ILIM to interrupt or PFSM

trigger

79 µs

(1) Input capacitors must be placed as close as possible to the device pins.

(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of the

capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of

regulators.

(3) Ceramic capacitors recommended

(4) Load transient voltage must be considered when selecting UV/OV threshold levels for the LDO output

(5) Additional capacitance, including local and POL, beyond the specifiied value can cause the LDO to become unstable

7.6 Low Noise Low Drop-Out Regulator (LDO4)

Over operating free-air temperature range (unlessotherwise noted). Voltage level refers to the thermal/ground pad of the

device.

POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Electrical Characteristics

2.1a C

IN(LDO4)

Input filtering

capacitance

(1)

Connected from PVIN_LDO4 to GND, Shared

input tank capacitance (depending on platform

requirements)

1 2.2 µF

2.1b C

OUT(LDO4)

Output filtering

capacitance

(2)

Connected from VOUT_LDO4 to GND 1 2.2 4 µF

2.1c C

ESR(LDO4)

Input and output capacitor

ESR

(3)

1 MHz ≤ f ≤ 10 MHz 20 mΩ

2.1d

OUT_TOTAL

(LDO4)

Total capacitance at output

(Local + POL)

(4)

1 MHz ≤ f ≤ 10 MHz, fast ramp 15 µF

2.1e 1 MHz ≤ f ≤ 10 MHz, slow ramp 30 µF

2.2 V

IN(LDO4)

LDO Input voltage 2.2 5.5 V

2.3 V

OUT(LDO4)

LDO output voltage

configurable range

with 25-mV steps 1.2 3.3 V

www.ti.com

TPS6593-Q1

SLVSE83 – DECEMBER 2020

ADVANCE INFORMATION

Submit Document Feedback

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7.6 Low Noise Low Drop-Out Regulator (LDO4) (continued)

Over operating free-air temperature range (unlessotherwise noted). Voltage level refers to the thermal/ground pad of the

device.

POS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

2.5 T

DCOV(LDO4)

Total DC output voltage

accuracy, including voltage

references, DC load and

line regulations, process

and temperature

IN(LDO4)

- V

OUT(LDO4)

> 300 mV –1% 1%

2.7 I

OUT(LDO4)

Output current V

IN(LDO4)min

≤ V

IN(LDO4)

≤ V

IN(LDO4)max

300 mA

2.8 I

SHORT(LDO4)

LDO current limit 400 900 mA

2.9

IN_RUSH(LDO4

)

LDO inrush current V

= 3.3V when LDO is enabled 650 mA

2.13a

PSRR

(LDO4)

Power supply ripple

rejection

f = 1 kHz, V

IN(LDO4)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

300 mA

2.13b

f = 10 kHz, V

IN(LDO4)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

= 300 mA

2.13c

f = 100 kHz, V

IN(LDO4)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

= 300 mA

2.13d

f = 1 MHz, V

IN(LDO4)

= 3.3 V, V

OUT

= 2.8 V, I

OUT

300 mA

2.12a

DIS(LDO4)

Pulldown discharge

resistance at LDO output

Active only when converter is

disabled, LDO4_PLDN = '00'

35 50 65 kΩ

2.12b

Active only when converter is

disabled, LDO4_PLDN = '01'

60 125 200 Ω

2.12c

Active only when converter is

disabled, LDO4_PLDN = '10'

120 250 400 Ω

2.12d

Active only when converter is

disabled, LDO4_PLDN= '11'

240 500 800 Ω

2.14 I

Qoff(LDO4)

Leackage current in off

mode

For all LDO regulators, VCCA = V

IN(LDO4)

= 3.8

V, T

= 25℃

2 µA

2.15 I

Qon(LDO4)

Quiescent current

LOAD

= 0 mA ,LDO4 under valid operating

condition

= 25℃

40 µA

2.16 T

LDR(LDO4)

Transient load regulation,

ΔV

OUT

IN(LDO4)

= 3.3V, V

OUT(LDO4)

= 2.80V, I

OUT

= 20%

of I

OUT_MAX

to 80% of I

OUT_MAX

in 1us,

OUT(LDO4)

= 2.2uF

–25 25 mV

2.17 T

LNR(LDO4)

Transient line regulation,

ΔV

OUT

/ V

OUT

On mode, not under dropout condition, V

step

= 600 mV

, t

= t

= 10 µs

-25 25 mV

2.18 V

NOISE(LDO4)

RMS Noise

100 Hz < f ≤ 100 kHz, V

= 3.3 V, V

OUT

= 1.8 V,

OUT

= 300 mA

15 µV

RMS

2.19

TH_SC_RV(LD

O4)

Threshold voltage for Short

Circuit and Residual

Voltage Detection

LDO4_EN = 0 140 150 160 mV

Timing Requirements

19.11

START(LDO4)

Start Time

Time from completion of enable command to

output voltage at 0.5 V

150 µs

19.12

RAMP(LDO4)

Ramp Time

Measured from 0.5 V to 90% of LDO4_VSET.

LDO4_SLOW_RAMP = 0

350 µs

19.12

Measured from 0.5 V to 90% of LDO4_VSET.

LDO4_SLOW_RAMP = 1

2.3 ms

19.12

RAMP_SLEW(L

DO4)

Ramp up slew rate

VOUT from 0.5 V to 90% of LDO4_VSET.

LDO4_SLOW_RAMP = 0

27 mV/µs

19.12

VOUT from 0.5 V to 90% of LDO4_VSET.

LDO4_SLOW_RAMP = 1

3 mV/µs

19.13

delay_OC(LDO

Over-current detection

delay

Detection singal delay when I

OUT

> ILIM 35 µs

TPS6593-Q1

SLVSE83 – DECEMBER 2020

www.ti.com

ADVANCE INFORMATION

20 Submit Document Feedback

Product Folder Links: TPS6593-Q1

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