内存屏障：硬件视角下的软件攻城者指南

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本文是一篇深入探讨内存屏障在多处理器系统（SMP）中的作用的论文，作者Paul E. McKenney，来自IBM Beaverton的Linux Technology Center。标题《MemoryBarriers: A Hardware View for Software Hackers》揭示了内存屏障对于软件设计者的重要性，尤其是在保证系统性能和可扩展性方面。首先，文章从CPU缓存的基本结构出发，解释了现代处理器如何通过缓存来提升执行效率。缓存的主要目的是存储近期频繁访问的数据，以减少对主内存的频繁读写，从而加快程序运行速度。然而，这带来了数据一致性的问题，因为多个处理器可能同时访问同一块内存区域，导致不同的缓存副本。为了确保所有处理器对内存的一致视图，文章讨论了缓存一致性协议，如 MESI (Modified, Exclusive, Shared, Invalid) 或 MOESI (Modified, Owned, Exclusive, Shared, Invalidated) 等，它们的作用是协调不同处理器之间的缓存状态，避免数据冲突和不一致。当一个处理器修改了缓存中的数据，这些协议会通知其他处理器同步更新，或者清除相关缓存，以维护全局数据的一致性。接下来，作者重点介绍了 store buffer 和 invalidate queue 的角色。Store buffer 负责暂存处理器写入缓存的数据，直到确认其他处理器已完成相应的操作后才写回主内存，这样可以减少不必要的内存操作。而 invalidate queue 则负责管理缓存失效的处理，当缓存数据被另一个处理器更新时，它会记录并确保后续的缓存查询返回正确的值。文章的核心观点是，内存屏障是由于CPU架构设计的内在需求产生的，它们的存在是为了应对缓存一致性带来的挑战，以维持系统的正确性和性能。尽管内存屏障可能会增加编程复杂性，但它们是实现高性能和可扩展多处理器系统不可或缺的部分。本文为软件开发者提供了一个硬件层面的视角，帮助他们理解内存屏障在现代计算机体系结构中的关键作用。

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Transition (d): The CPU does an atomic read-

modify-write operation on a data item that was

not present in its cache. It transmits a “read

invalidate”, receiving the data via a “read re-

sponse”. The CPU can complete the transition

once it has also received a full set of “invalidate

acknowledge” responses.

Transition (e): The CPU does an atomic read-

modify-write operation on a data item that was

previously read-only in its cache. It must trans-

mit “invalidate” messages, and must wait for a

full set of “invalidate acknowledge” responses be-

fore completing the transition.

Transition (f): Some other CPU reads the cache

line, and it is supplied from this CPU’s cache,

which retains a read-only copy. This transition

is initiated by the reception of a “read” message,

and this CPU responds with a “read response”

message containing the requested data.

Transition (g): Some other CPU reads a data item

in this cache line, and it is supplied either from

this CPU’s cache or from memory. In either case,

this CPU retains a read-only copy. This tran-

sition is initiated by the reception of a “read”

message, and this CPU responds with a “read re-

sponse” message containing the requested data.

Transition (h): This CPU realizes that it will soon

need to write to some data item in this cache

line, and thus transmits an “invalidate” message.

The CPU cannot complete the transition until

it receives a full set of “invalidate acknowledge”

responses. Alternatively, all other CPUs eject

this cache line from their caches via “writeback”

messages (presumably to make room for other

cache lines), so that this CPU is the last CPU

caching it.

Transition (i): Some other CPU does an atomic

read-modify-write operation on a data item in a

cache line held only in this CPU’s cache, so this

CPU invalidates it from its cache. This transi-

tion is initiated by the reception of a “read in-

validate” message, and this CPU responds with

both a “read response” and an “invalidate ac-

knowledge” message.

Transition (j): This CPU does a store to a data

item in a cache line that was not in its cache,

and thus transmits a “read invalidate” message.

The CPU cannot complete the transition until it

receives the “read response” and a full set of “in-

validate acknowledge” messages. The cache line

will presumably transition to “modiﬁed” state

via transition (b) as soon as the actual store com-

pletes.

Transition (k): This CPU loads a data item in

a cache line that was not in its cache. The

CPU transmits a “read” message, and completes

the transition upon receiving the corresponding

“read response”.

Transition (l): Some other CPU does a store to a

data item in this cache line, but holds this cache

line in read-only state due to its being held in

other CPUs’ caches (such as the current CPU’s

cache). This transition is initiated by the recep-

tion of an “invalidate” message, and this CPU

responds with an “invalidate acknowledge” mes-

sage.

Quick Quiz 4: How does the hardware handle the

delayed transitions described above?

2.4 MESI Protocol Example

Let’s now look at this from the perspective of a cache

line’s worth of data, initially residing in memory at

address 0, as it travels through the various single-line

direct-mapped caches in a four-CPU system. Table 1

shows this ﬂow of data, with the ﬁrst column show-

ing the sequence of operations, the second the CPU

performing the operation, the third the operation be-

ing performed, the next four the state of each CPU’s

cache line (memory address followed by MESI state),

and the ﬁnal two columns whether the corresponding

memory contents are up to date (“V”) or not (“I”).

Initially, the CPU cache lines in which the data

would reside are in the “invalid” state, and the data

is valid in memory. When CPU 0 loads the data at

address 0, it enters the “shared” state in CPU 0’s

cache, and is still valid in memory. CPU 3 also loads

the data at address 0, so that it is in the “shared”

state in both CPUs’ caches, and is still valid in mem-

ory. Next CPU 3 loads some other cache line (at

address 8), which forces the data at address 0 out of

its cache via a writeback, replacing it with the data

at address 8. CPU 2 now does a load from address 0,

but this CPU realizes that it will soon need to store

to it, and so it uses a “read invalidate” message in

order to gain an exclusive copy, invalidating it from

CPU 3’s cache (though the copy in memory remains

up to date). Next CPU 2 does its anticipated store,

changing the state to “modiﬁed”. The copy of the

data in memory is now out of date. CPU 1 does an

atomic increment, using a “read invalidate” to snoop

the data from CPU 2’s cache and invalidate it, so that

the copy in CPU 1’s cache is in the “modiﬁed” state

(and the copy in memory remains out of date). Fi-

nally, CPU 1 reads the cache line at address 8, which

uses a “writeback” message to push address 0’s data

back out to memory.

Note that we end with data in some of the CPU’s

caches.

Quick Quiz 5: What sequence of operations

would put the CPUs’ caches all back into the “in-

valid” state?

3 Stores Result in Unnecessary

Stalls

Although the cache structure shown in Figure 1 pro-

vides good performance for repeated reads and writes

from a given CPU to a given item of data, its perfor-

mance for the ﬁrst write to a given cache line is quite

poor. To see this, consider Figure 4, which shows a

timeline of a write by CPU 0 to a cacheline held in

CPU 1’s cache. Since CPU 0 must wait for the cache

line to arrive before it can write to it, CPU 0 must

stall for an extended period of time.

The time required to transfer a cache line from one CPU’s

cache to another’s is typically a few orders of magnitude more

than that required to execute a simple register-to-register in-

struction.

CPU 0 CPU 1

Write

Acknowledgement

Invalidate

Stall

Figure 4: Writes See Unnecessary Stalls

But there is no real reason to force CPU 0 to stall

for so long — after all, regardless of what data hap-

pens to be in the cache line that CPU 1 sends it, CPU

0 is going to unconditionally overwrite it.

3.1 Store Buﬀers

One way to prevent this unnecessary stalling of writes

is to add “store buﬀers” between each CPU and its

cache, as shown in Figure 5. With the addition of

these store buﬀers, CPU 0 can simply record its write

in its store buﬀer and continue executing. When the

cache line does ﬁnally make its way from CPU 1 to

CPU 0, the data will be moved from the store buﬀer

to the cache line.

However, there are complications that must be ad-

dressed, which are covered in the next two sections.

3.2 Store Forwarding

To see the ﬁrst complication, a violation of self-

consistency, consider the following code with vari-

ables “a” and “b” both initially zero, and with the

cache line containing variable “a” initially owned by

CPU 1 and that containing “b” initially owned by

CPU 0:

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