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IMX219 数据手册datastreet imx219是索尼800万像素中,超越imx179的一款对角为4.6mm (1/4.0型) , 有效像素约808万的背照式cmos图像传感器。imx219面向移动终端 (智能手机, 平板电脑) , 可以拍摄帧率180帧/秒高速视频的cmos图像传感器。imx219满足了高性能拍照应用所需的 [高灵敏度] 、[高帧率拍摄] 等基本功能需求, 由于芯片的小型化, 使得它即使在时尚的窄边框设计的设备的前置摄像头上也能很方便应用。
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1
Diagonal 4.60 mm (Type 1/4.0) 8 Mega-Pixel CMOS Image Sensor with Square Pixel for
Color Cameras
IMX219PQH5-C
Description
The IMX219PQH5-C is a diagonal 4.60 mm (Type 1/4.0) CMOS active pixel type image sensor with a square pixel
array and 8.08M effective pixels. This chip operates with three power supplies, analogue 2.8 V, digital 1.2 V, and IF
1.8 V, and has low power consumption. High sensitivity, low dark current, and no smear are achieved through the
adoption of R, G, and B primary color pigment mosaic filters. This chip features an electronic shutter with variable
charge-storage time.
In addition, this product is designed for use in cellular phone and tablet pc. When using this for another application,
Sony does not guarantee the quality and reliability of product. Therefore, don't use this for applications other than
cellular phone and tablet pc. Consult your Sony sales representative if you have any questions.
Features
◆ Back-illuminated CMOS image sensor Exmor R
TM
◆ 2-wire serial communication circuit on chip
◆ CSI2 serial data output (selection of 4lane/2lane)
◆ Timing generator, H and V driver circuits on chip
◆ CDS/PGA on chip
◆ 10-bit A/D converter on chip
◆ Automatic optical black (OB) clamp circuit on chip
◆ PLL on chip (rectangular wave)
◆ High sensitivity, low dark current, no smear
◆ Excellent anti-blooming characteristics
◆ Variable-speed shutter function (1 H units)
◆ R, G, B primary color pigment mosaic filters on chip
◆ Max. 30 frame/s in all-pixel scan mode
◆ Pixel rate: 280 [Mpixel/s] (All-pixels mode)
◆ 180 frame/s @720p with 2x2 analog (special) binning, 60 frame/s @1080p with V-crop
◆ Data rate: Max. 755 Mbps/lane(@4lane), 912Mbps/Lane(@2lane)
* Exmor R is a trademark of Sony Corporation. The Exmor R is a Sony's CMOS image sensor with significantly enhanced imaging
characteristics including sensitivity and low noise by changing fundamental structure of Exmor
TM
pixel adopted column parallel A/D converter
to back-illuminated type.
Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits.

IMX219PQH5-C
2
Device Structure
◆ CMOS image sensor
◆ Image size : Diagonal 4.60 mm (Type 1/4.0)
◆ Total number of pixels : 3296 (H) × 2512 (V) approx. 8.28 M pixels
◆ Number of effective pixels : 3296 (H) × 2480 (V) approx. 8.17 M pixels
◆ Number of active pixels : 3280 (H) × 2464 (V) approx. 8.08 M pixels
◆ Chip size : 5.095 mm (H) × 4.930 mm (V) (w/ Scribe)
◆ Unit cell size : 1.12 µm (H) × 1.12 µm (V)
◆ Substrate material : Silicon

IMX219PQH5-C
3
USE RESTRICTION NOTICE
This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the
image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may,
at any time, modify this Notice which will be available to you in the latest specifications book for the
Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its
own use restriction notice on the Products, such a use restriction notice will additionally apply between
you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or
distributor of Sony on such a use restriction notice when you consider using the Products.
Use Restrictions
The Products are intended for incorporation into such general electronic equipment as office products,
communication products, measurement products, and home electronics products in accordance with
the terms and conditions set forth in this specifications book and otherwise notified by Sony from time
to time.
You should not use the Products for critical applications which may pose a life- or injury- threatening
risk or are highly likely to cause significant property damage in the event of failure of the Products. You
should consult your sales representative beforehand when you consider using the Products for such
critical applications. In addition, you should not use the Products in weapon or military equipment.
Sony disclaims and does not assume any liability and damages arising out of misuse, improper use,
modification, use of the Products for the above-mentioned critical applications, weapon and military
equipment, or any deviation from the requirements set forth in this specifications book.
Design for Safety
Sony is making continuous efforts to further improve the quality and reliability of the Products; however,
failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care
to ensure the safe design of your products such as component redundancy, anti-conflagration features,
and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or
other social damage as a result of such failure.
Export Control
If the Products are controlled items under the export control laws or regulations of various countries,
approval may be required for the export of the Products under the said laws or regulations.
You should be responsible for compliance with the said laws or regulations.
No License Implied
The technical information shown in this specifications book is for your reference purposes only. The
availability of this specifications book shall not be construed as giving any indication that Sony and its
licensors will license any intellectual property rights in such information by any implication or otherwise.
Sony will not assume responsibility for any problems in connection with your use of such information or
for any infringement of third-party rights due to the same. It is therefore your sole legal and financial
responsibility to resolve any such problems and infringement.
Governing Law
This Notice shall be governed by and construed in accordance with the laws of Japan, without reference
to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating
to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the
court of first instance.
Other Applicable Terms and Conditions
The terms and conditions in the Sony additional specifications, which will be made available to you when
you order the Products, shall also be applicable to your use of the Products as well as to this
specifications book. You should review those terms and conditions when you consider purchasing
and/or using the Products.

IMX219PQH5-C
4
Contents
Description...................................................................................................................................................... 1
Features ......................................................................................................................................................... 1
Device Structure ............................................................................................................................................. 2
USE RESTRICTION NOTICE ......................................................................................................................... 3
1. Block Diagram and Pin Configuration...................................................................................................... 10
1-1 Block Diagram ................................................................................................................................... 10
1-2 Pin Description .................................................................................................................................. 10
1-3 Pin Equivalent Circuit ........................................................................................................................ 13
1-4 Chip Center, Optical Center and Pin Assignment ............................................................................... 14
1-5 Pin Coordinates................................................................................................................................. 15
2. Pixel Signal Output Specifications ........................................................................................................... 16
2-1 CSI-2 Signalling Mode ....................................................................................................................... 16
2-1-1 MIPI Transmitter .......................................................................................................................... 16
2-1-2 Output Lane ................................................................................................................................ 16
3. Control Registers .................................................................................................................................... 17
3-1 2-wire Serial Communication Operation Specifications ...................................................................... 17
3-1-1 Communication Protocol ............................................................................................................. 17
3-1-2 2-wire serial communication read/write operation supported ........................................................ 19
3-1-3 2-wire serial communication block characteristics ........................................................................ 23
3-1-4 2-wire serial communication register map .................................................................................... 24
3-1-5 Register Synchronization (Frame Bank) ...................................................................................... 25
3-2 2-wire Serial Communication Register Map (Configuration register, Parameter limit register) ..... 26
3-2-1 Configuration Registers – [0x0000-0x0FFF] ................................................................................ 26
3-2-2 Set-up Registers – [0x0100-0x0147] ........................................................................................... 28
3-2-3 Frame Bank Control and Group “A” – [0x0150-0x018D] ............................................................... 30
3-2-4 Frame Bank Control Group “B” – [0x0254-0x028D] ..................................................................... 32
3-2-5 Set-up Registers – [0x0300-0x0627] ........................................................................................... 33
3-3 Parameter Limit Registers – [0x1000-0x1FFF] (Read Only and Static) ............................................... 36
3-3-1 Integration Time and Gain Parameter Limit Registers – [0x1000-0x1301] .................................... 36
3-4 Manufacturer Specific Registers – [0x3000-0x5FFF] .......................................................................... 41
3-5 Frame Bank A and Bank B specific output samples ........................................................................... 43
4. Output Data Format ................................................................................................................................ 47
4-1 CSI-2 Output Data Format ................................................................................................................. 47
4-1-1 CSI-2 Output Data Channels ....................................................................................................... 47
4-1-2 CSI-2 Frame Structure ................................................................................................................ 47
4-1-3 Short Packet & Long Packet ........................................................................................................ 48
4-1-4 Data type .................................................................................................................................... 49

IMX219PQH5-C
5
4-1-5 CSI-2 Frame Format ................................................................................................................... 49
4-1-6 CSI-2 Embedded Data Line ......................................................................................................... 50
5-1 Pixel Array Physical Image ................................................................................................................ 52
5-2 Pixel Binning Mode ........................................................................................................................... 53
5-3 image size ......................................................................................................................................... 54
5-4 Readout Position ............................................................................................................................... 55
5-5 Frame Rate Calculation Formula ....................................................................................................... 56
5-6 Black Level Control ........................................................................................................................... 56
5-7 Storage Time (Electronic Shutter) Settings ........................................................................................ 56
5-7-1 Storage Time (Electronic Shutter) Setting Registers .................................................................... 56
5-7-2 Storage Time Calculation Method................................................................................................ 57
5-8 Gain Settings .................................................................................................................................... 58
5-8-1 Analogue Gain Settings............................................................................................................... 58
5-8-2 Digital gain settings ..................................................................................................................... 60
6. On Chip Image Processing ..................................................................................................................... 62
6-1 Test Pattern Generator ...................................................................................................................... 62
6-1-1 Test Pattern ................................................................................................................................ 62
6-2 Digital Gain Setting............................................................................................................................ 67
6-3 Black Level Adjust ............................................................................................................................. 67
6-4 Defect Correction .............................................................................................................................. 67
6-5 Pixel Re-alignment H Direction .......................................................................................................... 67
6-6 Pixel Re-alignment V Direction .......................................................................................................... 68
7. NVM Memory Map.................................................................................................................................. 69
7-1 Block Diagram ................................................................................................................................... 69
7-2 NVM Functions ................................................................................................................................. 69
7-3 Related Registers .............................................................................................................................. 70
7-4 NVM Memory Map ............................................................................................................................ 72
7-5 Defects Address registration .............................................................................................................. 75
7-5-1 Single defect address .................................................................................................................. 75
7-5-2 Same Color Adjoining defect address .......................................................................................... 75
7-5-3 2x4 defect address ...................................................................................................................... 75
7-5-4 Example Setting .......................................................................................................................... 76
8. How to operate IMX219PQH5-C ............................................................................................................. 77
8-1 Power on sequence ............................................................................................................................. 77
8-2 Power off sequence ............................................................................................................................. 79
9. Other Functions ...................................................................................................................................... 81
9-1 Clock System .................................................................................................................................... 81
9-1-1 Clock Structure ........................................................................................................................... 81
9-1-2 EXCK_FREQ setting depend on INCK frequency ........................................................................ 81
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