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SD Specifications Part A2 SD Host Controller Simplified Specification Version 4.20 April 10, 2017
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SD Specifications
Part A2
SD Host Controller
Simplified Specification
Version 4.20
April 10, 2017
Technical Committee
SD Association
©Copyright 2002-2017 SD Association
SD Host Controller Simplified Specification Version 4.20
i
Revision History
Date
Version
Changes compared to previous issue
April 3, 2006
1.00
Host Controller Simplified Specification Version 1.00
February 8, 2007
2.00
Host Controller Simplified Specification Version 2.00
February 25, 2011
3.00
Host Controller Simplified Specification Version 3.00
(1) UHS-I Support
(2) Shared Bus Support
April 10, 2017
4.20
Host Controller Simplified Specification Version 4.20
(1) UHS-II Support
(2) ADMA3 Support
(3) 64-bit System Addressing Support
To the extent this proposed specification, which is being submitted for review under the IP Policy,
implements, incorporates by reference or refers to any portion of versions 1.0 or 1.01 of the SD
Specifications (including Parts 1 through 4), adoption of the proposed specification shall require
Members utilizing the adopted specification to obtain the appropriate licenses from the SD-3C,
LLC, as required for the utilization of those portion(s) of versions 1.0 or 1.01 of the SD
Specifications.
For example, implementation of the SD Specifications in a host device under versions 1.0 or
1.01 and under the adopted specification requires the execution of an SD Host Ancillary License
Agreement with the SD-3C, LLC; and implementation of the SD Specifications under versions
1.0 or 1.01 and under the proposed specification in an SD Card containing any memory storage
capability (other than for storage of executable code for a controller or microprocessor within the
SD Card) requires the execution of an SD Memory Card License Agreement with the SD-3C,
LLC.
©Copyright 2002-2017 SD Association
SD Host Controller Simplified Specification Version 4.20
ii
Release of SD Simplified Specification/Addendum
The following conditions apply to the release of the SD Simplified Specification/Addendum by the SD
Card Association. The Simplified Specification/Addendum is a subset of the complete version of SD
Specification/Addendum that is owned by the SD Card Association.
Conditions for publication
Publisher and Copyright Holder:
SD Card Association
2400 Camino Ramon, Suite 375
San Ramon, CA 94583 USA
Telephone: +1 (925) 275-6615,
Fax: +1 (925) 886-4870
E-mail: office@sdcard.org
Notes:
This Simplified Specification/Addendum is provided on a non-confidential basis subject to the
disclaimers below. Any implementation of the Simplified Specification/Addendum may require a license
from the SD Card Association or other third parties.
Disclaimers:
The information contained in the Simplified Specification/Addendum is presented only as a standard
Specification/Addendum for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without
any representations or warranties of any kind. No responsibility is assumed by the SD Card Association
for any damages, any infringements of patents or other right of the SD Card Association or any third
parties, which may result from its use. No license is granted by implication, estoppel or otherwise under
any patent or other rights of the SD Card Association or any third party. Nothing herein shall be
construed as an obligation by the SD Card Association to disclose or distribute any technical
information, know-how or other confidential information to any third party.
©Copyright 2002-2017 SD Association
SD Host Controller Simplified Specification Version 4.20
iii
Conventions Used in This Document
Naming Conventions
Register names are shown in italic text such as Present State.
Names of bits or fields within registers are in bold text such as Buffer Write Enable.
Signal names are capitalized, bold and italic, followed by '#' if low active such as SDCD#.
Some terms are capitalized to distinguish their definition from their common English meaning. Words
not capitalized have their common English meaning.
Register names and the names of fields and bits in registers and headers are presented with the first
letter capitalized and the remainder in lower case.
Numbers and Number Bases
Hexadecimal numbers are written with a lower case "h" suffix, e.g., FFFFh and 80h.
Binary numbers are written with a lower case "b" suffix (e.g., 10b).
Binary numbers larger than four digits are written with a space dividing each group of four digits, as in
1000 0101 0010b.
All other numbers are decimal.
Key Words
May: Indicates flexibility of choice with no implied recommendation or requirement.
Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to
ensure interchangeability and to claim conformance with the specification.
Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give
strong consideration to such recommendations, but there is still a choice in implementation.
Special Terms
In this document, the following terms shall have special meaning:
Host Controller Refers to an SD Host Controller that complies with this Specification.
Host Driver Refers to the OS-specific driver for a Host Controller
Card Driver Refers to a driver for an SD/SDIO card or card function
Host System (or System) Refers to the entire system, such as a cellular phone, containing the Host
Controller
Implementation Notes
Some sections of this document provide guidance to Host Controller or Host Driver implementers. To
distinguish non-mandatory guidance from other parts of the SD Host Specification, it will be shown as
follows:
Implementation Note: This is an example of an implementation note.
©Copyright 2002-2017 SD Association
SD Host Controller Simplified Specification Version 4.20
iv
Table of Contents
1. Overview of the SD Standard Host ........................................................................................................... 1
1.1 Scope of the Standard SD Host .......................................................................................................... 1
1.2 Register Map ......................................................................................................................................... 2
1.3 Multiple Slot Support ........................................................................................................................... 3
1.4 Supporting DMA ................................................................................................................................... 3
1.5 SD Command Generation .................................................................................................................... 4
1.5.1 SD Mode Command Generation ..................................................................................................... 4
1.5.2 UHS-II Mode Command Generation ............................................................................................... 4
1.5.2.1 Command Issuing during CTS .................................................................................................. 5
1.5.2.2 Support of TID Check ................................................................................................................ 5
1.6 Suspend and Resume Mechanism (Version 3.00 or less) ................................................................ 5
1.7 Buffer Control ....................................................................................................................................... 6
1.7.1 Control of Buffer Pointer (Non DMA) ............................................................................................... 6
1.7.2 Determining Buffer Block Length ..................................................................................................... 8
1.7.3 Dividing Large Data Transfer ........................................................................................................... 8
1.8 Relationship between Interrupt Control Registers ........................................................................... 9
1.9 HW Block Diagram and Timing Part ................................................................................................. 11
1.10 Power State Definition of SD Host Controller ............................................................................... 12
1.11 Auto CMD12 ....................................................................................................................................... 13
1.12 Controlling SDCLK ........................................................................................................................... 14
1.13 Advanced DMA ................................................................................................................................. 15
1.13.1 ADMA Data Transfer between Host Controller and System Memory .......................................... 15
1.13.1.1 Block Diagram of ADMA2 ...................................................................................................... 15
1.13.1.2 An Example of ADMA2 Programming ................................................................................... 16
1.13.1.3 Data Address and Data Length Requirements ..................................................................... 16
1.13.2 General Descriptor Table Format ................................................................................................. 17
1.13.3 ADMA2 ......................................................................................................................................... 18
1.13.3.1 ADMA2 Descriptor Format .................................................................................................... 18
1.13.3.2 ADMA2 States ....................................................................................................................... 19
1.13.3.3 Stop/Continue Function during ADMA2 ................................................................................ 20
1.13.3.4 ADMA Error Status Register.................................................................................................. 21
1.13.4 ADMA3 ......................................................................................................................................... 22
1.13.4.1 ADMA3 States ....................................................................................................................... 23
1.13.4.2 Command Descriptor Format ................................................................................................ 24
1.13.4.3 Integrated Descriptor Format ................................................................................................ 25
1.13.4.4 Response Error Check During ADMA3 ................................................................................. 26
1.14 Test Registers ................................................................................................................................... 27
1.15 Block Count ....................................................................................................................................... 27
1.15.1 Selection of 16-bit or 32-bit Block Count ..................................................................................... 27
1.15.2 Block Count for Auto CMD23 ....................................................................................................... 27
1.15.3 Restriction of 16-bit Block Count ................................................................................................. 27
1.16 Sampling Clock Tuning .................................................................................................................... 28
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