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ug1037-vivado-axi-reference-guide Xilinx adopted the Advanced eXtensible Interface (AXI) protocol for Intellectual Property (IP) cores beginning with the Xilinx® Spartan®-6 and Virtex®-6 devices. Xilinx continues the use of the AXI protocol for IP targeting the UltraScale™ architecture, 7 series, and Zynq®-7000 All Programmable (AP) SoC devices. This document is intended to: Introduce key concepts of the AXI protocol. • Give an overview of what Xilinx tools you can use to create AXI-based IP. • Explain what features of AXI that have been adopted by Xilinx. • Provide guidance on how to migrate your existing design to AXI
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Vivado AXI Reference Guide www.xilinx.com 2
UG1037 (v4.0) July 15, 2017
Revision History
The following table shows the revision history for this document.
Date Version Revision
07/15/2017 4.0
Updated to match the new Vivado “Look and Feel”.
Updated all IP to reflect current features.
Added Zynq UltraScale+ MPSoC Processor Device in Chapter 3.
Added AXI SmartConnect IP in Chapter 3, and mention of SmartConnect IP
capabilities throughout the document.
Added AXI Verification IP in Chapter 3.
Added AXI4-Stream Verification IP in Chapter 3.
Added Zynq-7000 AP SoC Verification IP in Chapter 3.
06/24/2015 3.0
Added Quick Take Videos.
Updated the AXI IP Catalog Figure 2-1.
Updated the IP Project Settings Packaging tab in Figure 2-6.
Changed Features and Limitations in AXI Infrastructure IP Cores.
Updated Vivado Lab Tools to Vivado Lab Edition throughout the document.
Added XAPP1231 document reference to additional resources.
Added direct links to destinations.
11/20/2014 2.1
Corrected AWCACHE and ARCACHE for AXI4-Lite to “Signal not present” in
Appendix A, Write Data Channel Signals and Appendix A, Read Data Channel Signals.
11/19/2014 2.0
Changed:
IP Interoperability. Using Vivado AXI IP in RTL Projects.
Using the Create and Package IP Wizard for AXI IP.
Using Vivado IP Integrator to Assemble AXI IP.
Adding AXI IP to the IP Catalog Using Vivado IP Packager.
Using AXI IP in System Generator for DSP.
Added:
Adding AXI Interfaces Using High Level Synthesis.
AXI Virtual FIFO Controller. DataMover
Simulating IP. Using Debug and IP.
Performance Monitor IP. AXI BFM.
Bus Functional Models.
Choosing a Programmable Logic Interface.
Zynq-7000 All Programmable SoC Processor IP.
MicroBlaze Processor.
Added: Migrating to AXI for IP Cores.
Migrating to AXI for IP Cores.
Migrating HDL Designs to use DSP IP with AXI4-Stream.
Migrating IP Using the Vivado Create and Package Wizard.
High End Verification Solutions.
Added Optimizing AXI on Zynq-7000 AP SoC Processors.
04/02/2014 1.0
Initial release of Vivado AXI Reference Guide.
Send Feedback
Vivado AXI Reference Guide www.xilinx.com 3
UG1037 (v4.0) July 15, 2017
Table of Contents
Chapter 1: Introducing AXI for Vivado
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
What is AXI? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Summary of AXI4 Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
How AXI Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
IP Interoperability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Quick Take Videos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 2: AXI Support in Xilinx Tools and IP
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Using Vivado AXI IP in RTL Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Using the Create and Package IP Wizard for AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Adding AXI IP to the IP Catalog Using Vivado IP Packager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Using Vivado IP Integrator to Assemble AXI IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Using AXI IP in System Generator for DSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Adding AXI Interfaces Using High Level Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 3: Samples of Vivado AXI IP and Xilinx Processors
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AXI Infrastructure IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AXI4 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Simulating IP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Using Debug and IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Zynq UltraScale+ MPSoC Processor Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Zynq-7000 All Programmable SoC Processor IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
MicroBlaze Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Chapter 4: AXI Feature Adoption in Xilinx Devices
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Memory-Mapped IP Feature Adoption and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
AXI4-Stream Adoption and Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
DSP and Wireless IP: AXI Feature Adoption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Video IP: AXI Feature Adoption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Send Feedback
Vivado AXI Reference Guide www.xilinx.com 4
UG1037 (v4.0) July 15, 2017
Chapter 5: Migrating to Xilinx AXI Protocols
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Migrating to AXI for IP Cores. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Migrating IP Using the Vivado Create and Package Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Using System Generator for DSP for Migrating IP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Migrating a Fast Simplex Link to AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Migrating HDL Designs to use DSP IP with AXI4-Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
High End Verification Solutions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 6: AXI System Optimization: Tips and Hints
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
AXI System Optimization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
AXI4-based Vivado Multi-Ported Memory Controller: AXI4 System Optimization Example . . . . 126
Common Pitfalls Leading to AXI Systems of Poor Quality Results . . . . . . . . . . . . . . . . . . . . . . . . . 142
Optimizing AXI on Zynq-7000 AP SoC Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Chapter 7: AXI4-Stream IP Interoperability: Tips and Hints
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Key Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Domain Usage Guidelines and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Domain-Specific Data Interpretation and Interoperability Guidelines . . . . . . . . . . . . . . . . . . . . . 155
Appendix A: AXI Adoption Summary
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Global Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
AXI4 and AXI4-Lite Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
AXI4-Stream Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Appendix B: AXI Terminology
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Appendix C: Additional Resources and Legal Notices
Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Third-Party Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Xilinx Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Vivado Design Suite Video Tutorials. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Send Feedback
Vivado AXI Reference Guide www.xilinx.com 5
UG1037 (v4.0) July 15, 2017
Chapter 1
Introducing AXI for Vivado
Overview
Xilinx adopted the Advanced eXtensible Interface (AXI) protocol for Intellectual Property
(IP) cores beginning with the Xilinx
®
Spartan
®
-6 and Virtex
®
-6 devices. Xilinx continues
the use of the AXI protocol for IP targeting the UltraScale™ architecture, 7 series, and
Zynq
®
-7000 All Programmable (AP) SoC devices.
This document is intended to: Introduce key concepts of the AXI protocol.
• Give an overview of what Xilinx tools you can use to create AXI-based IP.
• Explain what features of AXI that have been adopted by Xilinx.
• Provide guidance on how to migrate your existing design to AXI.
Note:
This document is not intended to replace the advanced micro controller bus architecture
(AMBA
®
) ARM
®
AXI4 specifications. Before beginning an AXI design, you need to download, read,
and understand the AMBA AXI and ACE Protocol Specification, along with the AMBA4 AXI4-Stream
Protocol. You might need to fill out a brief registration before downloading the documents. See the
AMBA website [Ref 1].
Note: The ACE portion of the AMBA specification is generally not used, except in special cases such
as the connection between a MicroBlaze™ processor and its associated system cache block.
What is AXI?
AXI is part of ARM AMBA, a family of micro controller buses first introduced in 1996. The
first version of AXI was first included in AMBA 3.0, released in 2003. AMBA 4.0, released in
2010, includes the second major version of AXI, AXI4.
There are three types of AXI4 interfaces:
• AXI4: For high-performance memory-mapped requirements.
• AXI4-Lite: For simple, low-throughput memory-mapped communication (for example,
to and from control and status registers).
• AXI4-Stream: For high-speed streaming data.
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