© March 2009 Altera Corporation Power Delivery Network (PDN) Tool User Guide
1. Power Delivery Network (PDN) Tool
User Guide
Introduction
PCB designers must estimate the number, value, and type of decoupling capacitors
required to develop an efficient PCB decoupling strategy during the early design
phase, without going through extensive pre-layout simulations. The Altera’s Power
Delivery Network (PDN) tool provides these critical pieces of information.
The PDN tool is a Microsoft Excel-based spreadsheet tool used to calculate an
impedance profile based on user inputs. For a given power supply, the spreadsheet
requires only basic design information, such as the board stackup, transient current
information, and ripple specifications to come up with the impedance profile and the
optimum number of capacitors to meet the desired impedance target. The results
obtained through the spreadsheet tool are intended only as a preliminary estimate
and not as a specification. For an accurate impedance profile, Altera
®
recommends a
post-layout simulation approach using any of the available EDA tools, such as Sigrity
PowerSI, Ansoft SIWave, Cadence Allegro PCB PI, etc.
This version of the PDN tool is a general purpose tool for helping with the PCB
decoupling design. Altera has family-specific PDN tools for its FPGA devices that
help reduce over-design in PCB decoupling by taking the effects of device-related
parameters into consideration.
f For the availability of the PDN tool that targets your device, refer to the Altera website
at www.altera.com.
Application of the Tool
The purpose of the tool is to design a robust power delivery network by determining
an optimum number, type, and value of decoupling capacitors required to meet the
desired target impedance up to the target frequency. This spreadsheet tool is useful
for exploring the various what-if scenarios during the early design phase, without
extensive and time consuming pre-layout analysis.
PDN Decoupling Methodology Review
The PDN tool is based on a lumped equivalent model representation of the power
delivery network topology. Figure 1–1 shows a schematic representation of the circuit
topology, modeled as part of the tool.
PDN Circuit Topology
For first order analysis, the voltage regulator module (VRM) can be simply modeled
as a series-connected resistor and inductor, as shown in Figure 1–1. At low
frequencies, up to approximately 50 KHz, the VRM has a very low impedance and is
capable of responding to the instantaneous current requirements of the FPGA. The
ESR and ESL values can be obtained from the VRM manufacturer.
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