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最新版功率因数校正(PFC)手册(下).pdf
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最新版功率因数校正(PFC)手册是第一版PFC手册的升级版。通过一步一步的设计指导和系统级的对比,PFC手册评估了300W电源应用中
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PFC Handbook
http://onsemi.com
92
Circuit Schematics
L4
0. 2m
R2
2700k
PH 2
L1
0. 2m
PH 1
D2x
1N 4007
1
2
3
4
8
6
7
N C P1653
FB
Vctrl
In
CS
VCC
Drv
GND
Vm
X5
NCP1653
D1
1N 4007
R7
56k
C4
1nF
R3
470k
C1
100 nF /
63 V
C2
100nF
R8
100m / 3W
R4
2. 2k
R1
2200k
X1
SPP20N60
R17
10
PH 2
R15
10
R20x
10k
D3
1N 5817
R5
390
X2
SPP20N60
R18
10
R19
10k
R9
100m / 3W
R10
100m / 3W
RETURN
R13x
680k
R14
390k
R12
680k
R11
180k
C5
10nF
90 to 265 Vrms
5 0 or 60 Hz line volt a ge
C13
1 mF
Type = X2
CM 2
F1
10 A
LN Earth
C19
4. 7 nF
Type = Y2
C18
4. 7 nF
Type = Y2
C15
1mF
Type = X2
CM 1
C16
1mF
C17
1mF
R21x
680k
+
−
IN
X4
D iode bridge
RETURN
PH 1
28
C3
220nF
R6
100k
C6
22mF
R22x
680k
R23x
680k
C14
1 mF
Type = X2
C24
220nF
C25
22mF
M C 33152
NC
In A
GND
In B
NC
Ou tA
Ou tB
VCC
DRV1
R13
100
C27
100pF
DRV1
VCC 2
C28
220nF
VCC 2
VCC
DRV2
RETURN
RETURN
R24
2. 2k
CS
D5
1N 5406
Figure 7−10. Application Schematic
N
5
1
2
3
4
8
6
7
5
X7
SPP20N60
X3
SPP20N60
R23
10k
R22
10
R28
3
R25
15k
CS
D7
CSD10060
R28
3
R29
15k
CS
1N4148
D2
1N4148
D4
D8
CSD10060
V
out
R21
10k
R20
10
++
C11
330 m/450 V
C12
330 m/450 V
DRV2
DRV1
ON Semiconductor
http://onsemi.com
93
The performance of the board is captured in following waveforms and graphs. Figure 7−11 shows the typical waveforms
(line current, output voltage, current sense signal and rectified input voltage) for one branch at two line voltage conditions.
I
line
(10 A/div)
CS (negative sensing)
V
out
V
in,1
(input voltage for branch 1)
I
line
(10 A/div)
V
out
CS (negative sensing)
V
in,1
90 V
rms
230 V
rms
CS
V
out
V
in,1
(input voltage for branch 1)
90 V
rms
Figure 7−11. Typical Waveforms at Low Line (Left) and High Line (Right)
Plots of Figure 7−11 portray typical waveforms at full load (I
out
= 2.1 A). “CS” is the negative voltage provided by the current
sense transformers. It is representative of the current flowing into the MOSFETs of the two branches (“CS” is the common
output of the two current sense transformers). As expected, the input voltage of the “PH1 PFC stage” (“V
in,1
”) is a rectified
sinusoid for one half-line cycle and null for the other one. The line current is properly shaped.
Figure 7−12 provides a magnified view at the top of the line sinusoid. The switching frequency is 100 kHz. The signal
“V
sense
” (identical to “CS”) is a negative representation of the MOSFET current. The current sense transformers are wired so
that only the current drawn by the MOSFET drain is monitored (possible current flowing in the opposite direction cannot be
sensed).
The waveforms are similar to those of a traditional CCM PFC.
I
line
(10 A/div)
V
sense
(negative sensing)
V
out
V
in,1
(input voltage for branch 1)
I
line
(10 A/div)
V
out
V
sense
(negative sensing)
V
in,1
90 V
rms
230 V
rms
(negative sensing)
V
out
90 V
rms
230 V
rms
Figure 7−12. Magnified Views of Figure 7−11 Plots
Thermal measurements
The following results were obtained using a thermal camera, after a 1/2 hour operation. The board was operating at a 25°C
ambient temperature, without fan. These data are indicative.
For the bridge, the MOSFETs and diodes, the measurements were actually made on the heat-sink as near as possible to the
components of interest.
PFC Handbook
http://onsemi.com
94
Measurement Conditions:
V
in(rms)
= 88 V I
out
= 2 A
P
in(avg))
= 814 W PF = 0.995
V
out
= 381 V THD = 9 %
Devices Bridge MOSFET1 Diode1 Coil1 MOSFET2 Diode2 Coil2 Bulk Capacitor CM EMI coil
Temperature (5C) 85 95 77 47 86 80 48 40 45
Efficiency and Total Harmonic Distortion
Figure 7−13. Efficiency Performance
OUTPUT POWER (W)
100
98
96
94
92
90
100 200 300 800700400 600500
EFFICIENCY (%)
230 V
rms
120 V
rms
90 V
rms
20% P
max
P
max
20
100 200 300 800700400 600500
15
10
5
0
900
OUTPUT POWER (W)
THD (%)
Figure 7−14. Total Harmonic Distortion Over the
Load Range
230 V
rms
120 V
rms
90 V
rms
20% P
max
P
max
Figure 7−13 portrays the efficiency over the line range, from 20% to 100% of the load.
The efficiency was measured under following conditions:
♦
The measurements were made after the board was operated at full load, low line for 30 minutes
♦ All the measurements were made consecutively without interruptions
♦
PF, THD, I
in(rms)
were measured by a power meter PM1200
♦
V
in(rms)
was measured directly at the input of the board by a HP 34401A multimeter
♦ V
out
was measured by a HP 34401A multimeter
♦
The input power was computed according to: P
in(avg)
+ V
in(rms)
@ I
in(rms)
@ PF
♦ Open frame, ambient temperature, no fan
Reviewing Figure 7−13, it can be noted that:
♦
Like in a conventional PFC, the efficiency is higher at high line.
♦ At low line (90 V
rms
), full load, the efficiency is in the range of 94% without a fan. When measured @ 100 V
rms
input, full load efficiency of 95% was recorded.
♦
The light load efficiency is very good. For instance, at 20% of full load, efficiency is in the range of or higher than
96%. One of the reasons for this lies in the fact that a bridgeless PFC requires relatively low Qg MOSFETs
compared to a conventional PFC for the same efficiency target at full load.
Figure 7−14 portrays the THD at 90, 120 and 230 V
rms
over the load. One can note that the total harmonic distortion remains
very low even in high line, light load (<15%) where the line current is small and more sensitive to all the sources of distortion
like the system inaccuracies and mainly the EMI filter.
ON Semiconductor
http://onsemi.com
95
Conclusion
A bridgeless PFC based on the two-phase architecture has several merits among which one can list the ease of control or the
absence of high frequency noise injected to the line (eased EMI). In this chapter, the basics of the bridgeless architecture along
with a summary design procedure are covered. The designed prototype has been tested at full load (800-W output) without a
fan (open frame, ambient temperature). In these conditions, the full-load efficiency was measured in the range of 94% at 90
V
rms
and as high as 95% at 100 V
rms
. The THD remains very low. A NCP1653 or NCP1654-driven two-phase bridgeless PFC
is a solution of choice for very efficient, high power applications.
It should be noted that when traditional topologies (CCM/CrM/FCCrM boost) are scaled up to high power levels such as
800-W, they encounter several design challenges related to component size and dissipation. Hence, topologies such as
two-phase bridgeless or interleaved, which spread the heat dissipation and offer other benefits, make a lot of sense. Further
information on bridgeless PFC can be found in AND8392 [7] from ON Semiconductor.
Please note that a 300−W bridgeless PFC has been recently experimented. An application note is available on the ON
Semiconductor website that details this application [9].
PFC Handbook
http://onsemi.com
96
References
1. Laszlo Huber, Yungtaek Jang and Milan M. Jovanovic, “Performance Evaluation of Bridgeless PFC Boost
Rectifiers”, APEC 2007
2. Pengju Kong, Shuo Wang, and Fred C. Lee, “Common Mode EMI Noise Suppression for Bridgeless PFC
Converters”
3. Alexandre Ferrari de Souza and Ivo Barbi, “High Power Factor Rectifier with Reduced Conduction and
Commutation Losses”, Intelec, 1999
4. Joel Turchi, “Four Key Steps to Design a Continuous Conduction Mode PFC Stage Using the NCP1653”,
AND81842/D, ON Semiconductor, http://www.onsemi.com/pub/Collateral/AND8184D.PDF
5. Patrick Wang, “Four Key Steps to Design a Continuous Conduction Mode PFC Stage Using the NCP1654”,
AND8322/D, ON Semiconductor, http://www.onsemi.com/pub/Collateral/AND8322D.PDF
6. NCP1653 data sheet and application notes, www.onsemi.com
7. NCP1654 data sheet and application notes, www.onsemi.com
8. Joel Turchi, “A 800−W Bridgless PFC Stage”, AND8392/D, ON Semiconductor, http://www.onsemi.com/pub/
Collateral/AND8392−D.PDF
9. Joel Turchi, “A High−Efficiency, 300−W Bridgeless PFC Stage,”AND8481/D, ON Semiconductor,
http://www.onsemi.com/pub/Collateral/AND8481−D.PDF
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