stm32_QuadSPI_Flash.pdf

stm32

QuadSPI

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April 2020 AN4760 Rev 3 1/95

AN4760

Application note

Quad-SPI interface on STM32 microcontrollers and

microprocessors

Introduction

In order to manage a wide range of multimedia, richer graphics and other data-intensive

content, embedded applications evolve to offer more sophisticated features. These

sophisticated features require extra demands on the often limited micocontroller (MCU) and

microprocessor (MPU) on-chip memory.

The STM32 MCUs and MPUs will be referred to as STM32 devices in this document. The

devices that are concerned are listed in

Table 1: Applicable products

External parallel memories are used to extend the STM32 devices on-chip memory and

solve the memory size limitation. Usually this action compromises an increase in the pin

count and implies a more complex design.

To face these requirements, the STM32 devices embed an external memory interface

named Quad-SPI (see more details on

Table 2 on page 9). This interface allows the

connection of external compact-footprint Quad-SPI high-speed memories.This Quad-SPI

interface is used for data storage such as images, icons, or for code execution.

This application note describes the Quad-SPI interface on the STM32 devices and explains

how to use the module to configure, program, and read external Quad-SPI memory. It

describes some typical use cases to use the Quad-SPI interface based on some software

examples from the STM32Cube firmware package and from the STM32F7 Series

application notes.

For additional more detailed information about the products listed in the table below, refer to

the corresponding datasheets and reference manuals available from the STMicroelectronics

web site www.st.com.

Table 1. Applicable products

Type Products, lines and series

Microcontrollers

STM32F7 Series, STM32L4 Series

STM32F412, STM32F413/423, STM32F446, STM32F469/479,

STM32H743/753, STM32H750 Value line

STM32L4R5/S5, STM32L4R7/S7, STM32L4R9/S9

STM32WB55CC, STM32WB55CE, STM32WB55CG, STM32WB55RC,

STM32WB55RE, STM32WB55RG, STM32WB55VC, STM32WB55VE,

STM32WB55VG, STM32WB35CC, STM32WB35CE, STM32WB35CZ

Microprocessors STM32MP151x, STM32MP153x, STM32MP157x devices

www.st.com

Contents AN4760

2/95 AN4760 Rev 3

Contents

1 General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 QUADSPI availability and features across STM32 families . . . . . . . . . . . . 8

2.2 Quad-SPI benefits against classic SPI and parallel interfaces . . . . . . . . . 10

2.2.1 Main benefits of STM32 embedded Quad-SPI interface . . . . . . . . . . . . 10

2.3 QUADSPI in a smart architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.3.1 System architecture: STM32L4 Series . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.3.2 System architecture: STM32F4 Series . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.3.3 System architecture: STM32F7 Series . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.4 System architecture: STM32H7 Series . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.5 System architecture: STM32WB35xx and STM32WB55xx devices . . . 16

3 Quad-SPI interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Flexible frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.1 Instruction phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1.2 Address phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.3 Alternate-byte phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.1.4 Dummy-cycle phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.1.5 Data phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.2 Multiple hardware-configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.1 Single-SPI mode (classic SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2.2 Dual-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.2.3 Quad-SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.4 Dual-Flash memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.2.5 DDR and SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.3 Three operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.3.1 Indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.3.2 Status-flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.3.3 Memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.4 Special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4.1 Send instruction only-once (SIOO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4.2 Delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.4.3 Timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

AN4760 Rev 3 3/95

AN4760 Contents

3.4.4 Additional status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4.5 Busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4.6 4-byte address mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.4.7 QUADSPI and delay block in STM32H7 Series . . . . . . . . . . . . . . . . . . 35

3.5 Interrupts and DMA usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5.1 Interrupts usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.5.2 DMA usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.6 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4 QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.1 GPIOs configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.1.1 GPIOs configuration using STM32CubeMX tool . . . . . . . . . . . . . . . . . . 40

4.2 QUADSPI peripheral configuration and clock . . . . . . . . . . . . . . . . . . . . . 43

4.2.1 QUADSPI peripheral configuration (QUADSPI_CR register) . . . . . . . . 43

4.2.2 Quad-SPI Flash memory parameters configuration

(QUADSPI_DCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

4.2.3 QUADSPI and MPU configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.2.4 Quad-SPI memory device configuration . . . . . . . . . . . . . . . . . . . . . . . . 46

4.2.5 Starting a communication (QUADSPI_CCR register) . . . . . . . . . . . . . . 47

4.3 Hardware considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.3.1 Pull-up resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.3.2 Good PCB design allows maximum QUADSPI speed . . . . . . . . . . . . . 48

4.3.3 Chip-select high time (CSHT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

4.3.4 CKMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.3.5 Some considerations when using QUADSPI in classical SPI mode . . . 49

5 Programming Quad-SPI Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 50

5.1 Programming code or data for an end application . . . . . . . . . . . . . . . . . . 50

5.1.1 Programming Quad-SPI Flash memory using

the STM32 ST-LINK utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.1.2 Programming Quad-SPI Flash memory using IDE . . . . . . . . . . . . . . . . 55

5.2 Storing and erasing data on the fly during running application . . . . . . . . 59

5.2.1 Storing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.2.2 Erasing data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6 QUADSPI application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6.1 Reading data from Quad-SPI memory: graphical application . . . . . . . . . 62

Contents AN4760

4/95 AN4760 Rev 3

6.1.1 Frame buffer content generation from Quad-SPI memory . . . . . . . . . . . 62

6.1.2 Displaying images directly from the Quad-SPI memory . . . . . . . . . . . . 65

6.2 Executing from external Quad-SPI memory: extend internal memory size 67

6.2.1 Configuring Quad-SPI in Memory-mapped mode during system

initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

6.2.2 Placing application code in external Quad-SPI memory . . . . . . . . . . . . 73

6.3 Storing (programming) data on the fly during a running application . . . . . 79

6.3.1 QUADSPI indirect write: programming Quad-SPI memory using DMA . 79

6.3.2 QUADSPI indirect write: programming Quad-SPI memory using

interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

6.4 Erasing-data example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

6.5 Hardware implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

7 Performance and power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1 How to get the best performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1.1 Write performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.1.2 Read performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

7.2 Decreasing power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.2.1 Use timeout counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7.2.2 Put the Quad-SPI memory in Deep power-down mode . . . . . . . . . . . . . 90

7.2.3 Quad-SPI Flash memories supporting DPD mode . . . . . . . . . . . . . . . . 91

8 Supported devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

AN4760 Rev 3 5/95

AN4760 List of tables

List of tables

Table 1. Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. QUADSPI availability and features across STM32 families . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 3. Benefits of using STM32 Quad-SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 4. Instruction phase configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. Address-phase configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. Alternate-byte phase configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. Data phase configuration versus Quad-SPI functional modes . . . . . . . . . . . . . . . . . . . . . . 22

Table 8. Hardware configurations versus used GPIO number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 9. Dual-Flash memory hardware configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 10. Additional status bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 11. BUSY bit reset in different Quad-SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 12. Address mode versus maximum addressable memory space . . . . . . . . . . . . . . . . . . . . . . 35

Table 13. QUADSPI interrupts summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 14. DMA requests mapping and transfer directions versus STM32 series . . . . . . . . . . . . . . . . 37

Table 15. Execution performances versus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table 16. Different STM32 boards embedding Quad-SPI Flash memory . . . . . . . . . . . . . . . . . . . . . 85

Table 17. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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