ARMv8-A架构参考手册：ARM官方ARMv8汇编指令详解

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ARM Architecture Reference Manual ARMv8 是ARM官方发布的针对ARMv8-A架构的详细技术文档，它提供了系统级的ARM指令集指导，是深入理解和学习ARM汇编编程的权威参考书籍。该手册版权归属ARM Limited及其关联公司，自2013年至2017年期间更新，强调了非保密性质，但同时也声明了其内容受知识产权保护，未经ARM明确书面许可，不得以任何形式复制或实施。手册的重要内容包括： 1. **ARMv8架构介绍**：文档详细介绍了ARMv8架构，这是ARM体系结构的一个重要版本，特别针对ARMv8-A架构设计，支持广泛的嵌入式系统和移动设备应用。 2. **汇编指令详解**：手册涵盖了ARMv8架构下的汇编指令集，包括但不限于数据类型、运算符、控制转移、内存访问等，对于程序员来说，这是编写高效、优化代码的基础。 3. **处理器特性**：文档详细描述了ARMv8-A架构特有的特性，如64位指令集、内存管理单元(MMU)增强、虚拟化支持、SMMU（System Management Mode Unit）等，这些都是现代处理器的核心功能。 4. **安全特性和扩展性**：ARMv8对安全性有所强化，涉及TrustZone、Secure EL（安全执行环境）、硬件辅助加密等方面，以及对新硬件扩展的支持，如FPU（浮点运算单元）和NEON（向量处理单元）。 5. **许可证和保密条款**：在阅读和使用手册时，用户必须接受不能未经授权复制或商业用途的协议，这表明ARM对于其技术的严谨态度和对知识产权的尊重。 6. **版本历史和发布信息**：手册提供了一系列的版本发布记录，展示了ARM对于文档持续更新和完善的努力，反映了技术发展的最新趋势。通过阅读这份ARMv8 Architecture Reference Manual，开发者可以全面掌握ARM架构的最新特性，提升编程效率，同时确保遵循严格的版权和使用规定。这份文档是任何从事ARM平台开发的工程师必备的学习资料。

Preface

About this manual

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About this manual

This manual describes the ARM

architecture v8, ARMv8. The architecture describes the operation of an

ARMv8-A Processing element (PE), and this manual includes descriptions of:

• The two Execution states, AArch64 and AArch32.

• The instruction sets:

— In AArch32 state, the A32 and T32 instruction sets, that are compatible with earlier versions of the

ARM architecture.

— In AArch64 state, the A64 instruction set.

• The states that determine how a PE operates, including the current Exception level and Security state, and in

AArch32 state the PE mode.

• The Exception model.

• The interprocessing model, that supports transitioning between AArch64 state and AArch32 state.

• The memory model, that defines memory ordering and memory management. This manual covers a single

architecture profile, ARMv8-A, that defines a Virtual Memory System Architecture (VMSA).

• The programmers’ model, and its interfaces to System registers that control most PE and memory system

features, and provide status information.

• The Advanced SIMD and floating-point instructions, that provide high-performance:

— Single-precision, half-precision, and double-precision floating-point operations.

— Conversions between double-precision, single-precision, and half-precision floating-point values.

— Integer, single-precision floating-point, half-precision floating-point, and in A64, double-precision

vector operations in all instruction sets.

— Single-precision, half-precision, and double-precision floating-point vector operations in the A64

instruction set.

• The security model, that provides two security states to support secure applications.

• The virtualization model, that support the virtualization of Non-secure operation.

• The Debug architecture, that provides software access to debug features.

This manual gives the assembler syntax for the instructions it describes, meaning that it describes instructions in

textual form. However, this manual is not a tutorial for ARM assembler language, nor does it describe ARM

assembler language, except at a very basic level. To make effective use of ARM assembler language, read the

documentation supplied with the assembler being used.

This manual is organized into parts:

Part A Provides an introduction to the ARMv8-A architecture, and an overview of the AArch64 and

AArch32 Execution states.

Part B Describes the application level view of the AArch64 Execution state, meaning the view from EL0.

It describes the application level view of the programmers’ model and the memory model.

Part C Describes the A64 instruction set, that is available in the AArch64 Execution state. The descriptions

for each instruction also include the precise effects of each instruction when executed at EL0,

described as unprivileged execution, including any restrictions on its use, and how the effects of the

instruction differ at higher Exception levels. This information is of primary importance to authors

and users of compilers, assemblers, and other programs that generate ARM machine code.

Part D Describes the system level view of the AArch64 Execution state. It includes details of the System

registers, most of which are not accessible from EL0, and the system level view of the programmers’

model and the memory model. This part includes the description of self-hosted debug.

Preface

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Part E Describes the application level view of the AArch32 Execution state, meaning the view from the

EL0. It describes the application level view of the programmers’ model and the memory model.

Note

In AArch32 state, execution at EL0 is execution in User mode.

Part F Describes the T32 and A32 instruction sets, that are available in the AArch32 Execution state. These

instruction sets are backwards-compatible with earlier versions of the ARM architecture. This part

describes the precise effects of each instruction when executed in User mode, described as

unprivileged execution or execution at EL0, including any restrictions on its use, and how the effects

of the instruction differ at higher Exception levels. This information is of primary importance to

authors and users of compilers, assemblers, and other programs that generate ARM machine code.

Note

User mode is the only mode where software execution is unprivileged.

Part G Describes the system level view of the AArch32 Execution state, that is generally compatible with

earlier versions of the ARM architecture. This part includes details of the System registers, most of

which are not accessible from EL0, and the instruction interface to those registers. It also describes

the system level view of the programmers’ model and the memory model.

Part H Describes the Debug architecture for external debug. This provides configuration, breakpoint and

watchpoint support, and a Debug Communications Channel (DCC) to a debug host.

Part I Describes additional features of the architecture that are not closely coupled to a processing element

(PE), and therefore are accessed through memory-mapped interfaces. Some of these features are

OPTIONAL.

Part J Provides pseudocode that describes various features of the ARMv8 architecture.

Part K, Appendixes

Provide additional information. Some appendixes give information that is not part of the ARMv8

architectural requirements. The cover page of each appendix indicates its status.

Preface

Using this manual

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Using this manual

The information in this manual is organized into parts, as described in this section.

Part A, Introduction and Architecture Overview

Part A gives an overview of the ARMv8-A architecture profile, including its relationship to the other ARM PE

architectures. It introduces the terminology used to describe the architecture, and gives an overview of the

Executions states, AArch64 and AArch32. It contains the following chapter:

Chapter A1 Introduction to the ARMv8 Architecture

Read this for an introduction to the ARMv8 architecture.

Part B, The AArch64 Application Level Architecture

Part B describes the AArch64 state application level view of the architecture. It contains the following chapters:

Chapter B1 The AArch64 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch64 state. It describes execution at EL0 when EL0 is using AArch64 state.

Chapter B2 The AArch64 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch64 state. It describes the memory model for execution in EL0 when EL0 is using AArch64

state. It includes information about ARM memory types, attributes, and memory access controls.

Part C, The A64 Instruction Set

Part C describes the A64 instruction set, that is used in AArch64 state. It contains the following chapters:

Chapter C1 The A64 Instruction Set

Read this for a description of the A64 instruction set and common instruction operation details.

Chapter C2 About the A64 Instruction Descriptions

Read this to understand the format of the A64 instruction descriptions.

Chapter C3 A64 Instruction Set Overview

Read this for an overview of the individual A64 instructions, that are divided into five functional

groups.

Chapter C4 A64 Instruction Set Encoding

Read this for a description of the A64 instruction set encoding.

Chapter C5 The A64 System Instruction Class

Read this for a description of the AArch64 system instructions and register descriptions, and the

system instruction class encoding space.

Chapter C6 A64 Base Instruction Descriptions

Read this for information on key aspects of the A64 base instructions and for descriptions of the

individual instructions, which are listed in alphabetical order.

Chapter C7 A64 Advanced SIMD and Floating-point Instruction Descriptions

Read this for information on key aspects of the A64 Advanced SIMD and floating-point instructions

and for descriptions of the individual instructions, which are listed in alphabetical order.

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Part D, The AArch64 System Level Architecture

Part D describes the AArch64 state system level view of the architecture. It contains the following chapters:

Chapter D1 The AArch64 System Level Programmers’ Model

Read this for a description of the AArch64 state system level view of the programmers’ model.

Chapter D2 AArch64 Self-hosted Debug

Read this for an introduction to, and a description of, self-hosted debug in AArch64 state.

Chapter D3 The AArch64 System Level Memory Model

Read this for a description of the AArch64 state system level view of the general features of the

memory system.

Chapter D4 The AArch64 Virtual Memory System Architecture

Read this for a system level view of the AArch64 Virtual Memory System Architecture (VMSA),

the memory system architecture of an ARMv8 implementation that is executing in AArch64 state.

Chapter D5 The Performance Monitors Extension

Read this for a description of an implementation of the ARM Performance Monitors, that are an

optional non-invasive debug component.

Chapter D6 The Generic Timer in AArch64 state

Read this for a description of the AArch64 view of an implementation of the ARM Generic Timer.

Chapter D7 AArch64 System Register Descriptions

Read this for an introduction to, and description of, each of the AArch64 System registers.

Part E, The AArch32 Application Level Architecture

Part E describes the AArch32 state application level view of the architecture. It contains the following chapters:

Chapter E1 The AArch32 Application Level Programmers’ Model

Read this for an application level description of the programmers’ model for software executing in

AArch32 state. It describes execution at EL0 when EL0 is using AArch32 state.

Chapter E2 The AArch32 Application Level Memory Model

Read this for an application level description of the memory model for software executing in

AArch32 state. It describes the memory model for execution in EL0 when EL0 is using AArch32

state. It includes information about ARM memory types, attributes, and memory access controls.

Part F, The AArch32 Instruction Sets

Part F describes the T32 and A32 instruction sets, that are used in AArch32 state. It contains the following chapters:

Chapter F1 The AArch32 Instruction Sets Overview

Read this for an overview of the T32 and A32 instruction sets.

Chapter F2 About the T32 and A32 Instruction Descriptions

Read this to understand the format of the T32 and A32 instruction descriptions.

Chapter F3 T32 Instruction Set Encoding

Read this for a description of the T32 instruction set encoding. This includes the T32 encoding of

the Advanced SIMD and floating-point instructions.

Chapter F4 A32 Instruction Set Encoding

Read this for a description of the A32 instruction set encoding. This includes the A32 encoding of

the Advanced SIMD and floating-point instructions.

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Chapter F5 T32 and A32 Base Instruction Set Instruction Descriptions

Read this for a description of each of the T32 and A32 base instructions.

Chapter F6 T32 and A32 Advanced SIMD and floating-point Instruction Descriptions

Read this for a description of each of the T32 and A32 Advanced SIMD and floating-point

instructions.

Part G, The AArch32 System Level Architecture

Part G describes the AArch32 state system level view of the architecture. It contains the following chapters:

Chapter G1 The AArch32 System Level Programmers’ Model

Read this for a description of the AArch32 state system level view of the programmers’ model for

execution in an Exception level that is using AArch32.

Chapter G2 AArch32 Self-hosted Debug

Read this for an introduction to, and a description of, self-hosted debug in AArch64 state.

Chapter G3 The AArch32 System Level Memory Model

Read this for a system level view of the general features of the memory system.

Chapter G4 The AArch32 Virtual Memory System Architecture

Read this for a description of the AArch32 Virtual Memory System Architecture (VMSA).

Chapter G5 The Generic Timer in AArch32 state

Read this for a description of the AArch32 view of an implementation of the ARM Generic Timer.

Chapter G6 AArch32 System Register Descriptions

Read this for a description of each of the AArch32 System registers.

Part H, External Debug

Part H describes the architecture for external debug. It contains the following chapters:

Chapter H1 About External Debug

Read this for an introduction to external debug, and a definition of the scope of this part of the

manual.

Chapter H2 Debug State

Read this for a description of debug state, which the PE might enter as the result of a Halting debug

event.

Chapter H3 Halting Debug Events

Read this for a description of the external debug events referred to as Halting debug events.

Chapter H4 The Debug Communication Channel and Instruction Transfer Register

Read this for a description of the communication between a debugger and the PE debug logic using

the Debug Communications Channel and the Instruction Transfer register.

Chapter H5 The Embedded Cross-Trigger Interface

Read this for a description of the embedded cross-trigger interface.

Chapter H6 Debug Reset and Powerdown Support

Read this for a description of reset and powerdown support in the Debug architecture.

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