低功耗设计面临的问题与挑战

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Foreword

Energy consumption is a major, if not the major, concern today. The world is facing phenomenal growth of

demand for energy from the Far East coupled with the unabated and substantial appetite for energy in the

US and Europe. At the same time, population growth, economic expansion and urban development will

create greater demand for more personal-mobility items, appliances, devices and services. Recognizing

these worrisome trends, the U.S. Department Of Energy (DOE) has identified the reduction of energy

consumption in commercial and residential buildings as a strategic goal. The Energy Information

Administration at DOE attributed 33% of the primary energy consumption in the United States to building

space heating and cooling—an amount equivalent to 2.1 billion barrels of oil. At these levels, even a modest

aggregate increase in heating ventilation and air conditioning (HVAC) efficiency of 1% will provide direct

economic benefits to people, enabling reduction and better management of electric utility grid demand, and

reducing dependence on fossil fuels. In addition to the global relevance of efficient energy usage, there are

the micro-economic and convenience concerns of families, where energy consumption is putting pressure on

domestic budgets and where battery life of home mobile appliances is becoming a major selection factor for

consumers.

What can electronics makers do to help? Energy usage can be optimized at the chip, board, box, system, and

network level. At each of these levels there are major gains that can be achieved. Low-power design has been

a substantial research theme for years in IC design. Several important results have been used to limit energy

consumption by fast components such as microprocessors and digital signal processors. However, while the

trend has been improving, the energy consumption of, for example, Intel and AMD microprocessors is still

very important

, so that additional research is warranted. As we traverse layers of abstractions towards

systems and networks, the attention paid to low energy consumption is not increasing proportionally; an

important issue to consider moving forward on the energy conservation path.

Companies should take a holistic view in the energy debate. By carefully managing the interactions between

the different layers of abstraction and by performing a global trade-off analysis, companies may take a

leadership position. We understand that at this time, enough attention has not been paid to energy

consumption as the design goals have been centered on performance and cost. We also believe that no one

company or institution acting alone can tackle all the issues involved. Leveraging the supply chain, EDA

companies, partners’ research organizations and Universities offers a way to corral the available resources

and focus on the problem.

Focusing on the IC design area, process engineers cannot solve the problem alone: 90nm and smaller

process nodes are burning more power with increased design complexity and clock frequencies. Static power

is becoming the predominant source of energy waste. It is up to the design, EDA and IP community to create

methodologies that support better designs, higher performance, lower costs and higher engineering

productivity, in the context of low power.

I applaud the efforts of Cadence and the Power Forward Initiative members to develop, in a very a short

period of time, a methodology that uses the Common Power Format. Partners and competitors alike worked

closely across the entire design and manufacturing ecosystem, from advanced designers of low-power SoCs,

to EDA vendors, to foundries, to IP vendors, to ASIC vendors, to design service companies. They all

recognized the serious needs and formulated a working solution.

I believe that this guide will be a fundamental reference for designers and will help the world in saving a

substantial amount of energy!

Dr. Alberto Sangiovanni-Vincentelli, Professor, The Edgar L. and Harold H. Buttner

Chair of Electrical Engineering, University Of California, Berkeley, Co-founder, CTA

and Member of the Board, Cadence Design Systems.

Preface

In 2005, it was clear that power had become the most critical issue facing designers of electronic products.

Advanced process technology was in place, power reduction techniques were known and in use, but design

automation and its infrastructure lagged. Low-power design flows were manual, error-prone, risky, and

expensive. The pressure to reduce power was ever more pervasive and the methodologies available were

undesirable.

Recognizing this burgeoning design automation and infrastructure problem, Cadence as the EDA leader took

the initiative to tackle this crisis. To solve the broader design problem holistically, the effort had to involve

the entire electronic product development design chain, including systems and EDA companies, IP suppliers,

foundries, ASIC and design services companies as well as test companies. In May of 2006, we teamed up

with 9 other industry leaders to form the Power Forward Initiative (PFI) to address the obstacles to lower-

power IC design. Within Cadence, technologists from over 15 business groups realized that to incorporating

an efficient, automated low-power design solution into existing design flows would require, significant

innovation in every step of the design flow. Through intensive collaboration across the team, it was

concluded that implementing advanced power reduction techniques could be best facilitated by a separate,

comprehensive definition of power intent that could be applied at each step in the design, verification and

implementation stages. The Common Power Format was born.

The founding members of PFI: Applied Materials, AMD, ARM, ATI, Freescale, Fujitsu, NEC Electronics,

NXP, and TSMC came together with Cadence to devise, refine and validate the holistic, CPF-enabled design,

verification and implementation methodology. From the very outset, the goal was to quickly enable the rapid

deployment of a design automation solution that comprehends power at every stage of the design process.

The scope of the R&D effort was huge, spanning software and algorithmic technology innovation, solution

kits, methodology development, and challenging software validation problems. The vision was simple but

success depended on execution at a scope never attempted before in the history of EDA.

Starting in 2006, the founding companies of PFI created and reviewed the CPF specification. They then

initiated proof point projects that validated design flows using the Cadence® Low Power Solution with

complex designs and power intent specified in CPF. By the fall of 2006, PFI members completed validation

of a robust methodology and CPF specification and it was ready for broad deployment and standardization.

The CPF specification was publicly contributed to the Si2 Low Power Coalition (LPC) in December 2006. In

March 2007, it became a Si2 standard, open and freely available to everyone in the industry. Since then, the

Si2 LPC has continued to investigate new opportunities for CPF and plot out the evolution of this holistic

low-power format. With a growing movement towards developing greener electronic products, interest in

PFI, the Si2 LPC, and the adoption of CPF-enabled methodology continues to expand rapidly. A uniform

vision and belief in the energy efficient electronic products drove the industry-wide team at an accelerated

pace.

The result, A Practical Guide to Low Power Design, embodies the collective intellectual work and experience

of some of the best engineers in the electronics industry. Our goal in developing this living, web-based book

is to share our experience with the world’s design community. As new designs are completed, new chapters

in low-power design will be written and added to the guide.

Finally, I want to acknowledge all the people involved in this effort. This diverse pan-industry team of

dedicated individuals worked with passion and commitment to bring this solution to life. Working on a noble

cause that has positive and measurable impact on the state of the art in electronic design as well as positive

ramifications for the environment has been exciting for us all. Together, we have built an ecosystem to

accelerate low-power design.

Dr. Chi-Ping Hsu, Corporate Vice President, IC Digital and Power Forward, Cadence

Design Systems.

Acknowledgements

This book has been made possible by the personal passion and commitment of scores of dedicated people.

We would like to offer our thanks and gratitude to these individuals from companies in the Power Forward

Initiative for the countless hours spent in reviewing the CPF specification, providing feedback, and engaging

in complex proof point projects to validate CPF-enabled design flows. We will attempt to acknowledge many

of them here, but for each mentioned, there are numerous others on their teams who worked diligently to

make CPF, CPF-based low-power design methodology and ultimately this book a reality.

Special thanks go to Toshiyuki Saito from NEC Electronics as his vision inspired this book project. He

articulated the need to capture the collective Power Forward Initiative experiences in one place to make

them available for the benefit of the broader electronics design community.

We thank the founding members of the Power Forward Initiative — ATI, AMD, Applied Materials, ARM,

Freescale, Fujitsu, NEC, NXP, and TSMC — for having the vision to recognize the challenges of low-power

design and the commitment to work on developing a holistic low-power intent specification.

Special thanks also go to those companies who engaged in early proof point projects, with a nascent CPF

specification, to validate the solution for low power design. We are grateful for the hard work of engineering

teams at ARC, AMD, ARM, Freescale, Fujitsu, NEC, NXP, and TSMC for their CPF-based design projects.

We express our gratitude to the following individuals and to their companies for contributing the resources

to participate in the Power Forward Initiative; that work served as the basis for this book.

ARC International Karl Aucker, Gagan Gupta, Colin Holehouse

ARM, Inc. Keith Clarke, Joe Convey, John Goodenough

AMD Corporation Ed Chen, Dan Shimizu, Ward Vercruysse, Gill Watt

Cadence Design Systems Mohit Bhatnagar, Pinhong Chen, Yonghao Chen, John Decker, Phil

Giangarra, Mitch Hines, Anand Iyer, Lisa Jensen, Tony Luk, Pankaj

Mayor, Michael Munsey, Koorosh Nazifi, Rich Owen, Susan

Runowicz-Smith, Saghir Shaikh, Randy Shay, Tim Yu, Qi Wang Tony

Willis, William Winkler

Calypto Design Anmol Mathur, Devadas Varma

Faraday Lee Chu, C. J. Hsieh, Chung Ho, Albert Chen

Freescale Semiconductor Arijit Dutta, Dave Gross, Milind Padhye, Joe Pumo

Fujitsu Electronics Yoshimi Asada, Tsutomu Nakamori

Globetech Solutions Stylianos Diamantidis

Global Unichip Corporation Albert Li, Kurt Huang

NEC Electronics Toshiyuki Saito, Hideyuki Okabe, Toshihiro Ueda,Hiroshi Kikuchi

NXP Semiconductors Barry Dennington, Herve Menager

Sequence Design Vic Kulkarni, Tom Miller

Si2 Nick English, Steve Schulz, Sumit Dasgupta

SMIC Feng Chen

Tensilica Ashish Dixit, Jagesh Sanghavi

TSMC Chris Ho, David Lan, L.C. Lu, Ed Wan

Virage Logic Oscar Siguenza, Manish Bhatia

Improv Systems Victor Berman

UMC Garry Shyu

We gratefully acknowledge Neyaz Khan, who developed the book outline and contributed the introduction

and verification chapters, Tim Yu who contributed the front-end design chapter and Wei-Li Tan who

contributed the low-power implementation chapter. Special thanks to Holly Stump who was executive editor

for the book, her dedication and expertise contributed greatly to the entire project. And last but not least,

thanks to Susan Runowicz-Smith who tirelessly managed the entire project.

Table of Contents

Introduction to Low Power.......................................................................................6

Low Power Today................................................................................................6

Power Management ............................................................................................9

Complete Low-Power RTL-to-GDSII Flow Using CPF ......................................23

A Holistic Approach to Low-Power Intent ..........................................................31

Verification of Low-Power Intent with CPF............................................................32

Power Intent Validation .....................................................................................32

Low-Power Verification......................................................................................34

CPF Verification Summary ................................................................................50

Front-End Design with CPF ..................................................................................52

Architectural Exploration....................................................................................52

Synthesis Low-Power Optimization ...................................................................54

Automated Power Reduction in Synthesis.........................................................56

CPF-Powered Reduction in Synthesis ..............................................................62

Simulation for Power Estimation........................................................................72

CFP Synthesis Summary ..................................................................................75

Low-Power Implementation with CPF ...................................................................76

Introduction to Low-Power Implementation .......................................................76

Gate-Level Optimization in Power-Aware Physical Synthesis ...........................80

Clock Gating in Power-Aware Physical Synthesis.............................................80

Multi-V

Optimization in Power-Aware Physical Synthesis ...............................81

Multiple Supply Voltage (MSV) in Power-Aware Physical Synthesis.................82

Power Shutoff (PSO) in Power-Aware Physical Synthesis................................85

Dynamic Voltage/Frequency Scaling (DVFS) Implementation ..........................93

Substrate Biasing Implementation.....................................................................94

CPF Implementation Summary .........................................................................98

CPF User Experience ...........................................................................................99

ARC Energy PRO: Technology for Active Power Management ........................99

NEC Electronics: Integrating Power Awareness in SoC Design with CPF ......107

FUJITSU: CPF in the Low-Power Design Reference Flow..............................126

NXP User Experience: Complex SoC Implementation with CPF.....................143

References and Bibliography..............................................................................162

Low-Power Links.................................................................................................164

Power Forward Initiative..................................................................................164

Cadence Low-Power Links..............................................................................164

CPF Terminology Glossary.................................................................................165

Design Objects ................................................................................................165

CPF Objects ....................................................................................................165

Special Library Cells for Power Management..................................................166

Index ...................................................................................................................167

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