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ARM

Cortex

-M3 DesignStart

™

Eval

Revision: r0p0

FPGA User Guide

ARM 100896_0000_00_en

ARM

Cortex

-M3 DesignStart

™

Eval

FPGA User Guide

Release Information

Document History

Issue Date Confidentiality Change

0000-00 14 June 2017 Non-Confidential First release for r0p0

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LES-PRE-20349

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in

accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

ARM

Cortex

-M3 DesignStart

™

Eval

Non-Confidential

Contents

ARM

Cortex

-M3 DesignStart

™

Eval FPGA User

Guide

Preface

About this book ...................................................... ...................................................... 7

Feedback .................................................................................................................... 10

Chapter 1 Introduction

1.1 About Cortex

-M3 DesignStart

™

Eval ................................... ................................... 1-12

1.2 About the ARM Versatile Express Cortex-M Prototyping System (V2M-MPS2+) . . 1-14

1.3 Using the documentation ............................................ ............................................ 1-15

1.4 FPGA Evaluation Flow directory structure ............................... ............................... 1-17

1.5 Limitations ....................................................... ....................................................... 1-18

Chapter 2 Using the prebuilt FPGA image

2.1 Setting up the MPS2+ FPGA platform .................................. .................................. 2-20

2.2 Running the self-test program ........................................ ........................................ 2-21

2.3 Connecting to a debugger ........................................... ........................................... 2-23

Chapter 3 FPGA platform overview

3.1 System overview .................................................. .................................................. 3-25

3.2 Memory map ............................................................................................................ 3-26

3.3 Block RAM instances ............................................... ............................................... 3-27

3.4 External Zero Bus Turnaround SSRAM ................................. ................................. 3-28

3.5 External PSRAM ...................................................................................................... 3-29

Non-Confidential

3.6 Arduino adapter board .............................................. .............................................. 3-30

3.7 Embedded Trace Macrocell interface ...................................................................... 3-31

3.8 CMSDK APB subsystem ............................................ ............................................ 3-32

3.9 AHB GPIO ....................................................... ....................................................... 3-33

3.10 Serial Peripheral Interface ........................................... ........................................... 3-34

3.11 Color LCD parallel interface .......................................... .......................................... 3-35

3.12 Ethernet ......................................................... ......................................................... 3-36

3.13 VGA ............................................................ ............................................................ 3-37

3.14 Audio I

S ........................................................ ........................................................ 3-38

3.15 Audio configuration .................................................................................................. 3-40

3.16 FPGA system control and I/O .................................................................................. 3-41

Chapter 4 Clocks

4.1 Source clocks .......................................................................................................... 4-43

4.2 Derived clocks .................................................... .................................................... 4-44

Chapter 5 Serial Communication Controller

5.1 SCC interface overview ............................................. ............................................. 5-46

5.2 SCC memory map ................................................. ................................................. 5-47

Chapter 6 FPGA build

6.1 Build flow ........................................................ ........................................................ 6-50

6.2 Build requirements ................................................. ................................................. 6-52

Chapter 7 Integrating with mbed

™

7.1 Compatibility with mbed

™

OS ......................................... ......................................... 7-54

Chapter 8 Performance and utilization

8.1 Performance and clocks .......................................................................................... 8-56

8.2 Utilization of default system .......................................... .......................................... 8-57

Appendix A Revisions

A.1 Revisions - Cortex

-M3 DesignStart

™

Eval .................................................... Appx-A-59

Non-Confidential

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