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P2020处理器参考手册
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P2020 QorIQ Integrated Processor Reference Manual
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P2020 QorIQ Integrated Processor
Reference Manual
Supports: P2020 and P2010
Document Number: P2020RM
Rev. 2, 12/2012
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P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012
2 Freescale Semiconductor, Inc.
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Contents
Section number Title Page
Chapter 1
Overview
1.1 Overview.......................................................................................................................................................................67
1.1.1 Block diagram............................................................................................................................................67
1.1.2 Critical performance parameters................................................................................................................68
1.1.3 Chip-level features.....................................................................................................................................69
1.2 Application examples....................................................................................................................................................70
1.2.1 LTE and WiMax baseband application......................................................................................................70
1.2.2 Line card control plane application............................................................................................................71
1.3 Architecture overview...................................................................................................................................................72
1.3.1 e500v2 cores and memory unit..................................................................................................................72
1.3.2 e500 coherency module (ECM) and address map.....................................................................................73
1.3.3 Integrated security engine (SEC)...............................................................................................................74
1.3.4 Enhanced three-speed Ethernet controllers................................................................................................74
1.3.5 Universal serial bus (USB) 2.0..................................................................................................................76
1.3.6 Enhanced secure digital host controller.....................................................................................................76
1.3.7 Enhanced serial peripheral interface (eSPI)...............................................................................................77
1.3.8 DDR SDRAM controller...........................................................................................................................77
1.3.9 High speed I/O interfaces...........................................................................................................................78
1.3.9.1 PCI Express interfaces...........................................................................................................78
1.3.9.2 Serial RapidIO interfaces.......................................................................................................79
1.3.9.3 SGMII....................................................................................................................................79
1.3.9.4 High-speed interface multiplexing.........................................................................................79
1.3.10 Programmable interrupt controller (PIC)...................................................................................................80
1.3.11 DMA, I2C, DUART, and eLBC................................................................................................................80
1.3.12 Device boot locations.................................................................................................................................81
1.3.13 Boot sequencer...........................................................................................................................................82
P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012
Freescale Semiconductor, Inc. 3
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Section number Title Page
1.3.14 Power management....................................................................................................................................82
1.3.15 System performance monitor.....................................................................................................................82
Chapter 2
Memory Map
2.1 Overview.......................................................................................................................................................................83
2.2 Configuration, control, and status registers..................................................................................................................84
2.2.1 Accessing CCSR memory from the local processor..................................................................................85
2.2.2 Accessing CCSR memory from external masters......................................................................................85
2.2.3 Organization of CCSR space.....................................................................................................................86
2.2.3.1 General utilities registers.......................................................................................................86
2.2.3.1.1 General utilities register organization.............................................................87
2.2.3.2 Programmable interrupt controller registers..........................................................................88
2.2.3.3 Serial RapidIO registers.........................................................................................................89
2.2.3.4 Device-specific utilities registers...........................................................................................90
2.2.4 CCSR address map.....................................................................................................................................91
2.3 Local access windows...................................................................................................................................................94
2.3.1 Precedence of local access windows..........................................................................................................95
2.3.2 Configuring local access windows.............................................................................................................95
2.3.3 Distinguishing local access windows from other mapping functions........................................................95
2.3.4 Illegal interaction between local access windows and DDR chip selects..................................................96
2.3.5 Local address map example.......................................................................................................................96
2.4 Local access window registers......................................................................................................................................97
2.4.1 Local access window 0 base address register (LAW_LAWBARn)..........................................................99
2.4.2 Local access window 0 attribute register (LAW_LAWARn)....................................................................99
2.5 Address translation and mapping units.........................................................................................................................101
2.5.1 Address translation ....................................................................................................................................101
2.5.2 Outbound ATMUs.....................................................................................................................................102
2.5.3 Inbound ATMUs........................................................................................................................................103
2.5.3.1 Illegal interaction between inbound ATMUs and LAWs......................................................103
P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012
4 Freescale Semiconductor, Inc.
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Section number Title Page
Chapter 3
Signal Descriptions
3.1 Signals overview...........................................................................................................................................................105
3.2 Configuration signals sampled at reset.........................................................................................................................116
3.3 Output signal states during reset...................................................................................................................................118
Chapter 4
Reset, Clocking, and Initialization
4.1 Overview.......................................................................................................................................................................119
4.2 External signal descriptions..........................................................................................................................................119
4.2.1 System control signals...............................................................................................................................120
4.2.2 Clock signals..............................................................................................................................................121
4.3 Accessing configuration, control, and status registers..................................................................................................122
4.3.1 Updating CCSRBAR.................................................................................................................................122
4.3.2 Accessing alternate configuration space....................................................................................................123
4.3.3 Boot page translation.................................................................................................................................124
4.3.4 Boot sequencer...........................................................................................................................................124
4.4 Reset Memory Map/Register Definition.......................................................................................................................124
4.4.1 Configuration, control, and status registers base address register (Reset_CCSRBAR)............................125
4.4.2 Alternate configuration base address register (Reset_ALTCBAR)...........................................................126
4.4.3 Alternate configuration attribute register (Reset_ALTCAR)....................................................................126
4.4.4 Boot page translation register (Reset_BPTR)............................................................................................127
4.5 Functional description...................................................................................................................................................127
4.5.1 Reset operations.........................................................................................................................................127
4.5.1.1 Soft reset................................................................................................................................128
4.5.1.2 Hard reset...............................................................................................................................128
4.5.2 Power-on reset sequence............................................................................................................................128
4.5.3 Power-on reset configuration.....................................................................................................................130
4.5.3.1 System PLL ratio...................................................................................................................131
4.5.3.2 DDR PLL Ratio.....................................................................................................................132
P2020 QorIQ Integrated Processor Reference Manual, Rev. 2, 12/2012
Freescale Semiconductor, Inc. 5
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