Contents
1 Overview............................................................................................................................................................................................................................................... 6
1.1. Before you begin ..................................................................................................................................................................................................... 6
2 What is TrustZone? ............................................................................................................................................................................................................................ 7
2.1. TrustZone for Armv8-M ......................................................................................................................................................................................... 7
3 TrustZone in the processor ............................................................................................................................................................................................................. 8
3.1. Security states ......................................................................................................................................................................................................... 8
3.2. Switching between Security states ........................................................................................................................................................................ 8
3.3. Virtual address spaces .......................................................................................................................................................................................... 10
3.4. Physical address spaces ........................................................................................................................................................................................ 11
3.5. Data, instruction, and unified caches ................................................................................................................................................................... 13
3.6. Translation Lookaside Buffer ............................................................................................................................................................................... 14
3.7. SMC exceptions ..................................................................................................................................................................................................... 14
3.8. Secure virtualization ............................................................................................................................................................................................. 15
4 System architecture ......................................................................................................................................................................................................................... 18
4.1. Slave devices: peripherals, and memories ........................................................................................................................................................... 18
4.3 Enforcing isolation ......................................................................................................................................................................................... 19
4.4 Bus masters .................................................................................................................................................................................................... 20
4.5 M and R profile Arm processors ................................................................................................................................................................... 22
4.6 Interrupts ........................................................................................................................................................................................................ 22
4.7 Handling interrupts ....................................................................................................................................................................................... 23
4.8 Debug, trace, and profiling ............................................................................................................................................................................ 24
4.9 Other devices ................................................................................................................................................................................................. 26
4.10 Trusted Base System Architecture .............................................................................................................................................................. 27
5 Software architecture ........................................................................................................................................................................................................ 28
5.1 Top-level software architecture ................................................................................................................................................................... 28
5.1.1 Trusting the message? ................................................................................................................................................................................... 29
5.1.2 Scheduling ...................................................................................................................................................................................................... 29
5.1.3 OP-TEE ........................................................................................................................................................................................................... 29
5.2 Interacting with Non-secure virtualization ................................................................................................................................................. 30
5.3 Boot and the chain of trust ............................................................................................................................................................................ 31
5.4 Boot failures ................................................................................................................................................................................................... 33
5.5 Trusted Board Boot Requirements .............................................................................................................................................................. 33
5.6 Trusted Firmware .......................................................................................................................................................................................... 34
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