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PG-02829-001_v11.1 | October2020
CUDA C++ Programming Guide
Design Guide
CUDA C++ Programming Guide PG-02829-001_v11.1|iii
Table of Contents
Chapter1.Introduction........................................................................................................ 1
1.1.The Benefits of Using GPUs.....................................................................................................1
1.2.CUDA
®
: A General-Purpose Parallel Computing Platform and Programming Model....... 2
1.3.A Scalable Programming Model..............................................................................................3
1.4.Document Structure................................................................................................................. 5
Chapter2.Programming Model.......................................................................................... 7
2.1.Kernels.......................................................................................................................................7
2.2.Thread Hierarchy...................................................................................................................... 8
2.3.Memory Hierarchy...................................................................................................................10
2.4.Heterogeneous Programming................................................................................................11
2.5.Compute Capability................................................................................................................. 14
Chapter3.Programming Interface....................................................................................15
3.1.Compilation with NVCC.......................................................................................................... 15
3.1.1.Compilation Workflow...................................................................................................... 16
3.1.1.1.Offline Compilation.................................................................................................... 16
3.1.1.2.Just-in-Time Compilation..........................................................................................16
3.1.2.Binary Compatibility......................................................................................................... 17
3.1.3.PTX Compatibility..............................................................................................................17
3.1.4.Application Compatibility..................................................................................................17
3.1.5.C++ Compatibility..............................................................................................................18
3.1.6.64-Bit Compatibility..........................................................................................................18
3.2.CUDA Runtime........................................................................................................................ 19
3.2.1.Initialization.......................................................................................................................19
3.2.2.Device Memory................................................................................................................. 20
3.2.3.Device Memory L2 Access Management........................................................................ 23
3.2.3.1.L2 cache Set-Aside for Persisting Accesses............................................................23
3.2.3.2.L2 Policy for Persisting Accesses............................................................................ 23
3.2.3.3.L2 Access Properties.................................................................................................25
3.2.3.4.L2 Persistence Example............................................................................................25
3.2.3.5.Reset L2 Access to Normal...................................................................................... 26
3.2.3.6.Manage Utilization of L2 set-aside cache................................................................ 27
3.2.3.7.Query L2 cache Properties........................................................................................27
3.2.3.8.Control L2 Cache Set-Aside Size for Persisting Memory Access............................27
3.2.4.Shared Memory................................................................................................................ 27
3.2.5.Page-Locked Host Memory............................................................................................. 33
CUDA C++ Programming Guide PG-02829-001_v11.1|iv
3.2.5.1.Portable Memory....................................................................................................... 33
3.2.5.2.Write-Combining Memory......................................................................................... 33
3.2.5.3.Mapped Memory........................................................................................................ 34
3.2.6.Asynchronous Concurrent Execution.............................................................................. 35
3.2.6.1.Concurrent Execution between Host and Device.....................................................35
3.2.6.2.Concurrent Kernel Execution....................................................................................35
3.2.6.3.Overlap of Data Transfer and Kernel Execution...................................................... 36
3.2.6.4.Concurrent Data Transfers....................................................................................... 36
3.2.6.5.Streams...................................................................................................................... 36
3.2.6.6.CUDA Graphs............................................................................................................. 40
3.2.6.7.Events......................................................................................................................... 48
3.2.6.8.Synchronous Calls..................................................................................................... 49
3.2.7.Multi-Device System.........................................................................................................49
3.2.7.1.Device Enumeration...................................................................................................49
3.2.7.2.Device Selection.........................................................................................................50
3.2.7.3.Stream and Event Behavior...................................................................................... 50
3.2.7.4.Peer-to-Peer Memory Access.................................................................................. 51
3.2.7.5.Peer-to-Peer Memory Copy...................................................................................... 51
3.2.8.Unified Virtual Address Space.........................................................................................52
3.2.9.Interprocess Communication.......................................................................................... 52
3.2.10.Error Checking............................................................................................................... 53
3.2.11.Call Stack........................................................................................................................54
3.2.12.Texture and Surface Memory........................................................................................ 54
3.2.12.1.Texture Memory....................................................................................................... 54
3.2.12.2.Surface Memory.......................................................................................................63
3.2.12.3.CUDA Arrays............................................................................................................ 66
3.2.12.4.Read/Write Coherency.............................................................................................66
3.2.13.Graphics Interoperability................................................................................................66
3.2.13.1.OpenGL Interoperability...........................................................................................67
3.2.13.2.Direct3D Interoperability......................................................................................... 69
3.2.13.3.SLI Interoperability...................................................................................................74
3.2.14.External Resource Interoperability................................................................................75
3.2.14.1.Vulkan Interoperability.............................................................................................75
3.2.14.2.OpenGL Interoperability...........................................................................................83
3.2.14.3.Direct3D 12 Interoperability.................................................................................... 83
3.2.14.4.Direct3D 11 Interoperability.................................................................................... 89
3.2.14.5.NVIDIA Software Communication Interface Interoperability (NVSCI)....................96
3.3.Versioning and Compatibility................................................................................................100
CUDA C++ Programming Guide PG-02829-001_v11.1|v
3.4.Compute Modes.................................................................................................................... 102
3.5.Mode Switches...................................................................................................................... 102
3.6.Tesla Compute Cluster Mode for Windows.........................................................................103
Chapter4.Hardware Implementation............................................................................. 104
4.1.SIMT Architecture................................................................................................................. 104
4.2.Hardware Multithreading......................................................................................................106
Chapter5.Performance Guidelines.................................................................................107
5.1.Overall Performance Optimization Strategies.....................................................................107
5.2.Maximize Utilization.............................................................................................................. 107
5.2.1.Application Level.............................................................................................................107
5.2.2.Device Level....................................................................................................................108
5.2.3.Multiprocessor Level......................................................................................................108
5.2.3.1.Occupancy Calculator..............................................................................................110
5.3.Maximize Memory Throughput.............................................................................................111
5.3.1.Data Transfer between Host and Device...................................................................... 112
5.3.2.Device Memory Accesses...............................................................................................113
5.4.Maximize Instruction Throughput........................................................................................ 117
5.4.1.Arithmetic Instructions...................................................................................................117
5.4.2.Control Flow Instructions.............................................................................................. 122
5.4.3.Synchronization Instruction........................................................................................... 123
AppendixA.CUDA-Enabled GPUs....................................................................................124
AppendixB.C++ Language Extensions............................................................................125
B.1.Function Execution Space Specifiers.................................................................................. 125
B.1.1.__global__.......................................................................................................................125
B.1.2.__device__...................................................................................................................... 125
B.1.3.__host__..........................................................................................................................125
B.1.4.Undefined behavior........................................................................................................ 126
B.1.5.__noinline__ and __forceinline__..................................................................................126
B.2.Variable Memory Space Specifiers......................................................................................127
B.2.1.__device__...................................................................................................................... 127
B.2.2.__constant__.................................................................................................................. 127
B.2.3.__shared__..................................................................................................................... 127
B.2.4.__managed__................................................................................................................. 128
B.2.5.__restrict__.....................................................................................................................128
B.3.Built-in Vector Types............................................................................................................130
B.3.1.char, short, int, long, longlong, float, double...............................................................130
B.3.2.dim3................................................................................................................................ 131
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