NVMe SSD介绍.pdf

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Chapter 2

SSD Architecture and PCI Express Interface

K. Eshghi and R. Micheloni

Abstract Flash-memory-based solid-state disks (SSDs) provide faster random

access and data transfer rates than electromechanical drives and today can often

serve as rotating-disk replacements, but the host interface to SSDs remains a

performance bottleneck. PCI Express (PCIe)-based SSDs together with an emerging

standard called NVMe (Non-Volatile Memory express) promises to solve the

interface bottleneck.

This chapter walks the reader through the SSD block diagram, from the NAND

memory to the Flash controller (including wear leveling, bad block management,

and garbage collection). PCIe basics and different PCIe SSD architectures are

reviewed. Finally, an overview on the standardization effort around PCI Express

is presented.

2.1 Introduction

Creativity is just connecting things. When you ask creative people how they did something,

they feel a little guilty because they didn’t really do it, they just saw something. It seemed

obvious to them after a while.

– Steve Jobs

Solid-state drives promise to greatly enhance enterprise storage performance. While

electromechanical disk drives have continuously ramped in capacity, the rotating-

storage technology doesn’t provide the access-time or transfer-rate performance

required in demanding enterprise applications, including on-line transaction pro-

cessing, data mining, and cloud computing. Client applications are also in need of

K. Eshghi () • R. Micheloni

Enterprise Computing Division, Integrated Device Technology, Inc.,

San Jose, CA, USA

e-mail: kamyar.eshghi@alum.mit.edu; rino.micheloni@ieee.org

R. Micheloni et al., Inside Solid State Drives (SSDs), Springer Series

in Advanced Microelectronics 37, DOI 10.1007/978-94-007-5146-0

2 SSD Architecture and PCI Express Interface 21

external DC-DC converter can be added in order to derive the internal power supply,

or a quartz can be used for a better clock precision. Of course, reasonable ﬁlter

capacitors are inserted for stabilizing the power supply. It is also very common to

have a temp sensor for power management reasons. For data caching, a fast DDR

memory is frequently used: during a write access, the cache is used for storing data

before transfer to the Flash. The beneﬁt is that data updating, e.g. in routing tables,

is faster and does not wear out the Flash.

In order to improve performances, NANDs are organized in different Flash

channels, as shown in Fig. 2.1.

2.3 Non-volatile Memories

Semiconductor memories can be divided into two major categories: RAM (Random

Access Memories)andROM(Read Only Memories): RAMs lose their content

when power supply is switched off, while ROMs virtually hold it forever. A third

category lies in between, i.e. NVM (Non-Volatile Memories), whose content can be

electrically altered but it is also preserved when the power supply is switched off.

NVMs are more ﬂexible than the original ROM, whose content is deﬁned during

manufacturing and cannot be changed by the user anymore.

NVM’s history began in the 1970s, with the introduction of the ﬁrst EPROM

memory (Erasable Programmable Read Only Memory). In the early 1990s, Flash

memories came into the game and they started being used in portable products,

like mobile phones, USB keys, camcorders, and digital cameras. Solid State Disk

(SSD) is the latest killer application for Flash memories. It is worth mentioning that,

depending on how the memory cells are organized in the memory array, it is possible

to distinguish between NAND and NOR Flash memories. In this book we focus on

NAND memories as they are one of the basic elements of SSDs. NOR architecture

is described in great details in [4].

NAND Flash cell is based on the Floating Gate (FG) technology, whose cross

section is shown in Fig. 2.2. A MOS transistor is built with two overlapping gates

Control Gate (CG)

Drain (D)

Source (S)

Floating Gate (FG)

Tunnel Oxide (TOX)

Interpoly Oxide

(D) (B) (S)

(FG)

(CG)

Bulk (B)

Fig. 2.2 Schematic representation of a ﬂoating gate memory cell (left) and the corresponding

capacitive model (right)

22 K. Eshghi and R. Micheloni

rather than a single one: the ﬁrst one is completely surrounded by oxide, while

the second one is contacted to form the gate terminal. The isolated gate constitutes

an excellent “trap” for electrons, which guarantees charge retention for years. The

operations performed to inject and remove electrons from the isolated gate are called

program and erase, respectively. These operations modify the threshold voltage V

of the memory cell, which is a special type of MOS transistor. Applying a ﬁxed

voltage to cell’s terminals, it is then possible to discriminate two storage levels:

when the gate voltage is higher than the cell’s V

, the cell is on (“1”), otherwise it

is off (“0”).

It is worth mentioning that, due to ﬂoating gate scalability reasons, charge trap

memories are gaining more and more attention and they are described in Chap. 5,

together with their 3D evolution.

2.4 NAND Flash

2.4.1 NAND Array

A Flash device contains an array of ﬂoating-gate transistors: each of them acts as

memory cell. In Single Level Cell (SLC) devices, each memory cell stores one bit

of information; Multi-Level Cell (MLC) devices store 2 bits per cell.

The basic element of a NAND Flash memory is the NAND string, as shown

in Fig. 2.3a. Usually, a string is made up by 32 (M

to M

C31

), 64 or 128 cells

connected in series. Two selection transistors are placed at the edges of the string:

SSL

ensures the connection to the source line. M

DSL

connects the string to the

bitline BL. The cell’s control gates are connected through the wordlines (WLs).

Figure 2.3b shows how the matrix array is built starting from the basic string. In the

WL direction, adjacent NAND strings share the same WL, DSL, BSL and SL. In

the BL direction, two consecutive strings share the bitline contact. Figure 2.4 shows

a section of the NAND array along the bitline direction.

All the NAND strings sharing the same group of WL’s form a Block. In Fig. 2.3b

there are three blocks:

–BLOCK0ismadeupbyWL

< 31:0>;

–BLOCK1ismadeupbyWL

< 31:0>;

–BLOCK2ismadeupbyWL

< 31:0 > .

Logical pages are made up of cells belonging to the same WL. The number of

pages per WL is related to the storage capabilities of the memory cell. Depending

on the number of storage levels, Flash memories are referred to in different ways:

• SLC memories stores 1 bit per cell;

• MLC memories stores 2 bits per cell;

• 8LC memories stores 3 bits per cell;

• 16LC memories stores 4 bits per cell.

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