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Introduction
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1.2.7 Memory System
The optional memory system includes:
•A Bus Interface Unit (BIU) with a configurable AMBA 4 AXI interface that can support
a high-performance L2 memory system.
• An extended AHB-Lite interface to support low-latency system peripherals.
•A TCM Control Unit (TCU) with TCM interfaces that can support external ECC logic and
an AHB slave (AHBS) interface for system access to TCMs.
• Instruction cache and data cache units, with optional Error Correction Code (ECC).
•A Memory Built-in Self Test (MBIST) interface provided by the MBIST interface unit
(MIU). The memory system supports online MBIST, where the RAM arrays can be
accessed by the MBIST interface while the processor is running. MBIST is also supported
during production test.
See Chapter 5 Memory System for more information.
1.2.8 Store Buffer
The Store Buffer (STB) holds store operations when they have left the load/store pipeline and
have been committed by the DPU. From the STB, a store can request access to the cache RAM
in the DCU, request the BIU to initiate linefills, or request the BIU to write the data out on the
AXIM interface.
The STB can merge several store transactions into a single transaction if they are to the same
64-bit aligned address.
1.2.9 Memory Protection Unit
The optional MPU has configurable attributes for memory protection. It includes up to 16
memory regions and Sub Region Disable (SRD), enabling efficient use of memory regions. It
also has the ability to enable a background region that implements the default memory map
attributes. See Chapter 6 Memory Protection Unit for more information.
1.2.10 Cortex-M7 Processor and PPB ROM tables
The two ROM tables enable a debugger to identify and connect to CoreSight debug
components. See Chapter 9 Debug for more information.
1.2.11 Cross Trigger Interface Unit
The optional CTI enables the debug logic and ETM to interact with each other and with other
CoreSight components. See Chapter 10 Cross Trigger Interface.
1.2.12 ETM
The optional ETM provides instruction-only or instruction and data trace capabilities when
configured. See the ARM
®
CoreSight
™
ETM-M7 Technical Reference Manual for more
information.
1.2.13 Debug and trace components
• Configurable Breakpoint unit (FPB) for implementing breakpoints.