ARMCortex-M7内核编程技术说明文档(英文)_Cortex-M7

Cortex-M7

内核编程

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ARM DDI 0489D (ID082615)

ARM

Cortex

-M7 Processor

Revision r1p1

Technical Reference Manual

ID082615 Non-Confidential

ARM Cortex-M7 Processor

Technical Reference Manual

Release Information

The following changes have been made to this book.

Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information

contained in this document may be protected by one or more patents or pending patent applications. No part of this

document may be reproduced in any form by any means without the express prior written permission of ARM. No

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Your access to the information in this document is conditional upon your acceptance that you will not use or permit

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This document may include technical inaccuracies or typographical errors.

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Change history

Date Issue Confidentiality Change

25 April 2014 A Confidential First release for r0p0

05 December 2014 B Non-Confidential First release for r0p2

19 March 2015 C Non-Confidential First release for r1p0

07 July 2015 D Non-Confidential First release for r1p1

ID082615 Non-Confidential

Contents

ARM Cortex-M7 Processor Technical Reference

Manual

Preface

About this book .......................................................................................................... vii

Feedback .................................................................................................................... xi

Chapter 1 Introduction

1.1 About the Cortex-M7 processor ............................................................................... 1-2

1.2 Component blocks ................................................................................................... 1-6

1.3 Interfaces ............................................................................................................... 1-11

1.4 Supported standards ............................................................................................. 1-13

1.5 Design process ...................................................................................................... 1-14

1.6 Documentation ....................................................................................................... 1-15

1.7 Product revisions ................................................................................................... 1-16

Chapter 2 Programmers Model

2.1 About the programmers model ................................................................................ 2-2

2.2 Modes of operation and execution ........................................................................... 2-3

2.3 Instruction set summary ........................................................................................... 2-4

2.4 System address map ............................................................................................... 2-5

2.5 Exclusive monitor ..................................................................................................... 2-7

2.6 Processor core registers .......................................................................................... 2-8

2.7 Exceptions ............................................................................................................... 2-9

Chapter 3 System Control

3.1 About system control ............................................................................................... 3-2

3.2 Register summary .................................................................................................... 3-3

3.3 Register descriptions ............................................................................................... 3-6

Contents

ID082615 Non-Confidential

Chapter 4 Initialization

4.1 About Initialization .................................................................................................... 4-2

Chapter 5 Memory System

5.1 About the memory system ....................................................................................... 5-2

5.2 Fault handling .......................................................................................................... 5-3

5.3 Memory types and memory system behavior .......................................................... 5-5

5.4 AXIM interface ......................................................................................................... 5-6

5.5 AHB peripheral interface ........................................................................................ 5-22

5.6 AHB slave interface ............................................................................................... 5-30

5.7 TCM interfaces ...................................................................................................... 5-33

5.8 L1 caches .............................................................................................................. 5-37

Chapter 6 Memory Protection Unit

6.1 About the MPU ........................................................................................................ 6-2

6.2 MPU functional description ...................................................................................... 6-3

6.3 MPU programmers model ........................................................................................ 6-4

Chapter 7 Nested Vectored Interrupt Controller

7.1 About the NVIC ........................................................................................................ 7-2

7.2 NVIC functional description ..................................................................................... 7-3

7.3 NVIC programmers model ....................................................................................... 7-4

Chapter 8 Floating Point Unit

8.1 About the FPU ......................................................................................................... 8-2

8.2 FPU functional description ....................................................................................... 8-3

8.3 FPU programmers model ........................................................................................ 8-5

Chapter 9 Debug

9.1 About debug ............................................................................................................ 9-2

9.2 About the AHBD interface ........................................................................................ 9-7

9.3 About the FPB ......................................................................................................... 9-8

Chapter 10 Cross Trigger Interface

10.1 About the CTI ......................................................................................................... 10-2

10.2 Cortex-M7 CTI functional description .................................................................... 10-3

10.3 CTI programmers model ........................................................................................ 10-5

Chapter 11 Data Watchpoint and Trace Unit

11.1 About the DWT ...................................................................................................... 11-2

11.2 DWT functional description .................................................................................... 11-3

11.3 DWT programmers model ..................................................................................... 11-4

Chapter 12 Instrumentation Trace Macrocell Unit

12.1 About the ITM ........................................................................................................ 12-2

12.2 ITM functional description ...................................................................................... 12-3

12.3 ITM programmers model ....................................................................................... 12-4

Chapter 13 Fault detection and handling

13.1 About fault detection and handling ........................................................................ 13-2

13.2 Cache RAM protection ........................................................................................... 13-3

13.3 Logic protection ..................................................................................................... 13-6

Appendix A Revisions

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