To provide the most up-to-date information, the document revision on the World Wide Web is the most
current. A printed copy may be an earlier revision. To verify you have the latest information available, refer
to: http://freescale.com/
This document contains information for the complete S12XE-Family and thus includes a set of separate
flash (FTM) module sections to cover the whole family. A full list of family members and options is
included in the appendices.
This document contains information for all constituent modules, with the exception of the S12X CPU. For
S12X CPU information please refer to CPU12XV2 in the CPU12/CPU12X Reference Manual.
Revision History
Date
Revision
Level
Description
Aug, 2007 1.10
Updated NVM P-flash data retention spec.
Corrected IIC register bit names and FCTL reference.
Added further input leakage specification parameters
Corrected VDDA to VDDX diode spec.
Sep, 2007 1.11
Updated FTM sections
Corrected SPI register names in register listing. Corrected typos.
Added PARTIDs
Corrected TIM availability entries in derivative Table D-2
Oct, 2007 1.12
Added alternative 80QFP S12XEA256 option
Enhanced Termperature Sensor configuration description
Nov, 2007 1.13 XEG128 derivative changed from one 128K array to two 64K arrays
Dec, 2007 1.14
Updated XEG128 D-Flash size.
Clarified unimplemented ranges
Added STOP/WAIT functionality to Vector Tables
Added further 384K derivative
Updated DBG section
Jan,2008 1.15
Added further s12XES384 derivative
Updated FTM, DBG, SCI sections
May,2008 1.16
Figure B-3 Θ1 value corrected.
Added LVR minimum assert level
Enhanced RESET pin description.
IIC register name corrected
Corrected D-Flash size reference for XEG128
Changed module revision history tables to a unified format
Corrected corrupted formats
July, 2008 1.17
Added Module Run Idd Values
Added 3.3V expansion bus timing
Corrected NVM timing parameters
Changed IIC SCL Divider note
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