BCM5389：单芯片8端口SerDes千兆交换机技术详解

交换机

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"BCM5389技术手册是关于Broadcom公司的一款8端口千兆交换机芯片的详细技术文档。这款芯片集成了8个1.25 Gbps的SerDes/SGMII端口接口，用于连接外部的千兆PHYs或光纤模块，为桌面级的Gigabit Ethernet交换提供了成本最低的解决方案，适用于WebSmart应用。BCM5389是一款高度集成的解决方案，将高速交换系统的所有功能，如包缓冲器、媒体访问控制器（MACs）、地址管理和非阻塞交换控制器融合在一个单片0.13-µm CMOS设备中。该芯片符合IEEE 802.3系列标准，包括PAUSE帧和自动协商子部分，确保与所有行业标准的以太网、快速以太网和吉比特以太网设备兼容。" BCM5389芯片的关键特性包括： 1. **8端口SerDes/SGMII接口**：BCM5389提供8个1.25 Gbps速率的SerDes（串行收发器）/ SGMII（简化小型封装介质独立接口）端口，每个端口都设计用于连接外部的物理层（PHY）设备或光纤模块，实现高速数据传输。 2. **高度集成**：该芯片集成了交换机所需的所有核心功能，减少了对外部组件的需求，降低了整体系统成本。它包含了包缓冲器、MACs、地址管理单元以及一个非阻塞的交换控制器，使得数据处理更为高效。 3. **低功耗设计**：采用0.13微米的CMOS工艺制造，这种技术有助于降低芯片的能耗，提高能效，对于桌面级应用尤其重要。 4. **兼容性**：BCM5389遵循IEEE 802.3系列标准，包括802.3（以太网）、802.3u（快速以太网）、802.3ab（吉比特以太网）和802.3x（流量控制）。这确保了与各种标准网络设备的无缝配合，支持MAC控制的PAUSE帧和自动协商功能。 5. **WebSmart应用**：BCM5389适合于构建智能网络设备，如WebSmart交换机，这些设备具有基本的网络管理和监控功能，但比传统的企业级交换机更简单、成本更低。在硬件开发中，BCM5389芯片可以用于设计经济高效的桌面级千兆以太网交换机，或者用于需要高带宽和可靠性的网络设备。开发人员需要理解和掌握BCM5389的技术手册，以正确配置和优化其性能，确保与网络环境的兼容性和稳定性。此外，由于其高度集成，设计时还需考虑电源管理、散热设计以及与其他系统组件的接口设计。

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BCM5389 Data Sheet

07/08/08

Broadcom Corporation

Page xvi Document 5389-DS09-R

Table 69: Mirror Capture Control Register (Page 02h: Address 010h–011h) ..................................................91

Table 70: Ingress Mirror Control Register (Page 02h: Address 012h–013h) ...................................................92

Table 71: Ingress Mirror Divider Register (Page 02h: Address 014h–015h) ...................................................93

Table 72: Ingress Mirror MAC Address Register (Page 02h: Address 016h–01Bh) ........................................93

Table 73: Egress Mirror Control Register (Page 02h: Address 01Ch–01Dh) ..................................................94

Table 74: Egress Mirror Divider Register (Page 02h: Address 01Eh–01Fh) ...................................................95

Table 75: Egress Mirror MAC Address Register (Page 02h: Address 020h–025h) .........................................95

Table 76: ARL Control Registers (Page 04h)...................................................................................................96

Table 77: Global ARL Configuration Register (Page 04h: Address 00h).........................................................96

Table 78: BPDU Multicast Address Register (Page 04h: Address 04h-09h) ...................................................97

Table 79: Multiport Address 1 Register (Page 04h: Address 010h–015h).......................................................97

Table 80: Multiport Vector 1 Register (Page 04h: Address 016h–019h)..........................................................97

Table 81: Multiport Address 2 Register (Page 04h: Address 020h–025h).......................................................98

Table 82: Multiport Vector 2 Register (Page 04h: Address 026h–029h)..........................................................98

Table 83: ARL/VTBL Access Registers (Page 05h).........................................................................................99

Table 84: ARL Table Read/Write Control Register (Page 05h: Address 00h) ...............................................100

Table 85: MAC Address Index Register (Page 05h: Address 02h–07h)........................................................100

Table 86: ARL Table MAC/VID Entry 0 Register (Page 05h: Address 010h–017h) ......................................100

Table 87: ARL Table Data Entry 0 Register (Page 05h: Address 018h–019h)..............................................101

Table 88: ARL Table MAC/VID Entry 1 Register (Page 05h: Address 20h–27h) ..........................................103

Table 89: ARL Table Data Entry 1 Register (Page 05h: Address 028h–029h)..............................................103

Table 90: ARL Table Search Control Register (Page 05h: Address 030h)....................................................104

Table 91: ARL Search Address Register (Page 05h: Address 031h–302h) ..................................................105

Table 92: ARL Table Search MAC/VID Result Register (Page 05h: Address 033h–03Ah)...........................105

Table 93: ARL Table Search Data Result Register (Page 05h: Address 03Bh–03Ch)..................................106

Table 94: Internal Serial Port Page Summary................................................................................................107

Table 95: Internal Serial Port Registers (Page 010h–017h) ..........................................................................107

Table 96: MII Control Register (Page 010h-017h: Address 00h-01h)............................................................108

Table 97: MII Status Register (Page 010h-017h: Address 02h-03h) .............................................................109

Table 98: Auto-Negotiation Advertisement Register (Page 010h-017h: Address 08h-09h)...........................110

Table 99: Auto-Negotiation Link Partner Ability Register (Page 010h-017h: Address 0Ah-0Bh)...................111

Table 100:Auto-Negotiation Expansion Register (Page 010h-017h: Address 0Ch-0Dh)................................112

Table 101:Extended Status Register (Page 010h-017h: Address 01Eh-01Fh) ..............................................112

Table 102:SerDes/SGMII Control 1 Register (Page 010h-017h: Address 020h-021h)...................................113

Table 103:Analog Transmit Register (Page 010h-017h: Address 020h-021h, Block 1) .................................114

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Data Sheet BCM5389

07/08/08

Broadcom Corporation

Document 5389-DS09-R Page xvii

Table 104:SerDes/SGMII Control 2 Register (Page 010h-017h: Address 022h-023h) .................................. 114

Table 105:SerDes/SGMII Control 3 Register (Page 010h-017h: Address 024h-025h) .................................. 115

Table 106:SerDes/SGMII Status 1 Register (Page 010h-017h: Address 028h-029h) ................................... 116

Table 107:SerDes/SGMII Status 2 Register (Page 010h-017h: Address 02Ah-02Bh)................................... 117

Table 108:SerDes/SGMII Status 3 Register (Page 010h-017h: Address 02Ch–02Dh) ................................. 118

Table 109:BER/CRC Error Counter Register (Page 010h–017h: Address 02Eh-02Fh) ................................ 119

Table 110:PRBS Control Register (Page 010h–017h: Address 030h-031h).................................................. 119

Table 111:PRBS Status Register (Page 010h–017h: Address 032h-033h) ................................................... 120

Table 112:Pattern Generator Control Register (Page 010h–017h: Address 034h-035h)............................... 120

Table 113:Pattern Generator Status Register (Page 010h–017h: Address 036h-037h)................................ 121

Table 114:Force Transmit 1 Register (Page 010h–017h: Address 03Ah-30Bh) ............................................ 121

Table 115:Force Transmit 2 Register (Page 010h–017h: Address 03Ch-03Dh)............................................ 122

Table 116:Block Address Number (Page 010h-017h: Address 03Eh-03Fh).................................................. 122

Table 117:Port MIB Registers Page Summary............................................................................................... 123

Table 118:Page 020h–027h Port MIB Registers ............................................................................................ 123

Table 119:Page 030h QoS Registers............................................................................................................. 127

Table 120:QoS Global Control Register (Page 030h: Address 00h) .............................................................. 128

Table 121:QoS IEEE 802.1P Enable Register (Page 030h: Address 04h–05h) ............................................ 128

Table 122:QoS DiffServ Enable Register (Page 030h: Address 06h–07h).................................................... 129

Table 123:IEEE 802.1p Priority Map Register (Page 030h: Address 010h–013h)......................................... 129

Table 124:DiffServ Priority Map 0 Register (Page 030h: Address 030h–035h) ............................................. 130

Table 125:DiffServ Priority Map 1 Register (Page 030h: Address 036h–03Bh)............................................. 130

Table 126:DiffServ Priority Map 2 Register (Page 030h: Address 03Ch–041h)............................................. 131

Table 127:DiffServ Priority Map 3 Register (Page 030h: Address 042h–407h) ............................................. 132

Table 128:Ingress Port Priority ID Map Register Address Summary ............................................................. 132

Table 129:Ingress Port Priority ID Map Register (Page 030h: Address 050h–061h) ..................................... 133

Table 130:TX Queue Control Register (Page 030h: Address 080h) .............................................................. 133

Table 131:TX Queue Weight Register Queue[0:3] (Page 030h: Address 081h–084h).................................. 134

Table 132:Page 032h Trunking Registers...................................................................................................... 135

Table 133:MAC Trunk Control Register (Page 032h, Address 01h) .............................................................. 135

Table 134:Trunk Group Register (Page 032h, Address 090h–091h)............................................................. 136

Table 135:Page 040h Jumbo Frame Control Register ................................................................................... 137

Table 136:Jumbo Frame Port Mask Registers (Page 040h, Address 01h-04h)............................................. 137

Table 137:Jumbo MIB Good Frame Max Size Registers (Page 040h, Address 05h-06h) ............................. 138

Table 138:Broadcast Storm Suppression Register (Page 041h).................................................................... 139

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BCM5389 Data Sheet

07/08/08

Broadcom Corporation

Page xviii Document 5389-DS09-R

Table 139:Global Rate Control Register (Page 041h, Address 00h–03h) ......................................................139

Table 140:Port Rate Control Register Address Summary ..............................................................................142

Table 141:Port Rate Control Register (Page 041h, Address 010h–02Fh)......................................................142

Table 142:External PHY Registers (Serial Ports) Page Summary..................................................................144

Table 143:External PHY Registers (Serial Ports) (Page 080h–087h).............................................................144

Table 144:Global Registers (Maps to All Pages) ............................................................................................146

Table 145:SPI Data I/O Register (Maps to All Registers, Address 0F0h–0F7h).............................................146

Table 146:SPI Status Register (Maps to All Registers, Address 0FEh)..........................................................146

Table 147:Page Register (Maps to All Registers, Address 0FFh) ..................................................................146

Table 148:Absolute Maximum Ratings ...........................................................................................................147

Table 149:Recommended Operating Conditions............................................................................................147

Table 150:Electrical Characteristics................................................................................................................148

Table 151:Reset and Clock Timing.................................................................................................................149

Table 152:Serial Interface Output Timings .....................................................................................................150

Table 153:RvMII Mode Output Timings ..........................................................................................................151

Table 154:RvMII Mode Input Timings .............................................................................................................152

Table 155:RGMII Output Timing (Normal Mode) ............................................................................................153

Table 156:RGMII Output Timing (Delayed Mode) ..........................................................................................154

Table 157:RGMII Input Timing (Normal Mode)...............................................................................................155

Table 158:RGMII Input Timing (Delayed Mode) .............................................................................................156

Table 159:GMII Output Timing........................................................................................................................157

Table 160:GMII Input Timing ..........................................................................................................................158

Table 161:MDC/MDIO Timing (Slave Mode) ..................................................................................................159

Table 162:MDC/MDIO Timing (Master Mode) ................................................................................................159

Table 163:Serial LED Interface Timing ...........................................................................................................160

Table 164:SPI Timings....................................................................................................................................161

Table 165:EEPROM Timing............................................................................................................................162

Table 166:Thermal Characteristics .................................................................................................................163

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Data Sheet BCM5389

07/08/08

Broadcom Corporation

Document 5389-DS09-R Introduction Page 1

Section 1: Introduction

OVERVIEW

The BCM5389 is a single-chip, 8-port switch device. The device provides:

• 9-port non-blocking 10/100/1000 Mbps switch controller

• Eight ports with SerDes/SGMII interface for connection to external 10/100/1000-Mbps Ethernet transceiver or SerDes

interface connection to 1000 Mbps full-duplex fiber module

• Eight integrated gigabit MACs (GMACs)

• One GMII/RGMII/RvMII port for PHY-less connection to the management agent

• An integrated Motorola SPI-compatible interface

• High-performance integrated packet buffer memory

• An address-resolution engine

The GMACs support full-duplex and half-duplex modes for 10 Mbps and 100 Mbps and full-duplex for 1000 Mbps. Flow

control is supported in the half-duplex mode with backpressure. In full-duplex mode, IEEE 802.3x frame-based flow control

is supported. The GMACs are IEEE 802.3-compliant and support maximum frame sizes of 9.6 KB.

An integrated address-management engine provides address learning and recognition functions at maximum frame rates.

The address table provides capacity for learning up to 4K unicast addresses. Addresses are added to the table after

receiving an error-free packet.

AUDIENCE

This document is for designers interested in integrating the BCM5389 switch into their hardware designs and for others who

need specific data about the physical characteristics and operation of the BCM5389 switch.

DATA SHEET INFORMATION

The following notational conventions are used in this document:

• Signal names are shown in uppercase letters (such as DATA).

• A bar over a signal name indicates that it is active low (such as CE

• In register and signal descriptions, [n:m] indicates a range from bit n to bit m (such as [7:0] indicates bits 7 through 0,

inclusive).

• The use of R or Reserved indicates that a bit or a field is reserved by Broadcom for future use. Typically, R is used for

individual bits and Reserved is used for fields.

• Numerical modifiers such as K or M follow traditional usage (for example, 1 KB means 1,024 bytes, 100 Mbps [referring

to fast Ethernet speed] means 100,000,000 bps, and 133 MHz means 133,000,000 Hz).

Note: The RvMII/GMII/RGMII port is used as a IMP (Management) Port only. It is not available for a PHY or

network port connection.

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