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首页三星DDR3内存芯片规格说明书-K4B4G1646E
三星DDR3内存芯片规格说明书-K4B4G1646E
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"三星DDR存储芯片K4B4G1646Q-HYK0的相关技术文档" 三星的K4B4G1646Q-HYK0是一款4Gb DDR3 DRAM内存芯片,其设计和规格由三星电子有限公司提供。这款芯片属于DDR(Double Data Rate)内存系列,DDR3是DDR内存的第三代产品,它在时钟周期的上升沿和下降沿都能传输数据,从而显著提高了数据传输速率。DDR3内存比前一代DDR2内存具有更低的功耗和更高的性能。 文档的版本为Rev.1.1,发布于2016年6月。三星保留了对产品和信息进行更改而不另行通知的权利。这表明文档中的内容可能会随着产品的迭代而有所更新,用户在使用时应关注最新的技术资料。 此文档声明,所有提供的信息“按原样”提供,不包含任何形式的保证,包括但不限于适销性、特定用途适用性的默示保证。这意味着用户在使用这些产品时需自行承担风险,三星不对其性能或功能的稳定性做出承诺。 三星强调,其产品不适用于生命支持、重症监护、医疗、安全设备等应用,因为在这些领域产品故障可能导致生命或人身伤害。此外,这些产品也不适用于军事或国防应用,或可能受到特殊条款和规定约束的政府采购项目。 如果需要关于三星产品的最新更新或额外信息,用户应联系最近的三星办公室。文档还指出,所有提及的品牌名称、商标和注册商标均为各自所有者的财产,未在文档中授予任何知识产权许可。 该文档还包含了版权声明,表明内容的知识产权归三星电子所有。整体而言,K4B4G1646Q-HYK0是一款针对高性能计算、数据中心和服务器应用设计的内存芯片,其性能和可靠性是关键考虑因素,但不适用于对安全性要求极高的应用场景。
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- 12 -
datasheetK4B4G1646E DDR3L SDRAM
Rev. 1.1
[ Table 9 ] Single-ended AC & DC input levels for DQ and DM (1.35V)
NOTE :
1. For input only pins except RESET
, V
REF
= V
REFDQ
(DC)
2.See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 13.5 mV).
4. For reference: approx. VDD/2 +/- 13.5 mV.
5. These levels apply for 1.35 Volt operation only. If the device is operated at 1.5 V, the respective levels in JESD79-3 ( VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/
L.DQ(AC150), VIH/L.DQ(AC135), etc. ) apply. The 1.5 V levels (VIH/L.DQ(DC100), VIH/L.DQ(AC175), VIH/L.DQ(AC150), VIH/L.DQ(AC135), etc. ) do not apply when the
device is operated in the 1.35 voltage range.
[ Table 10 ] Single-ended AC & DC input levels for DQ and DM (1.5V)
NOTE :
1. For input only pins except RESET
, V
REF
= V
REFDQ
(DC)
2.See "Overshoot and Undershoot specifications" section.
3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than +/-1% VDD (for reference: approx. +/- 15 mV).
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135); VIH.DQ(AC175) value is used when Vref + 0.175V is referenced,
VIH.DQ(AC150) value is used when Vref + 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135); VIL.DQ(AC175) value is used when Vref - 0.175V is referenced,
VIL.DQ(AC150) value is used when Vref - 0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
9. V
REF
DQ
(DC) is measured relative to VDD at the same point in time on the same device
10. Optional in DDR3 SDRAM for DDR3-800/1066/1333/1600: Users should refer to the DRAM supplier data sheetand/or the DIMM SPD to determine if DDR3 SDRAM devices
support this option.
Symbol Parameter
DDR3L-800/1066 DDR3L-1333/1600 DDR3L-1866
Unit NOTE
Min. Max. Min. Max. Min. Max.
1.35V
V
IH.DQ
(DC90)
DC input logic high
V
REF
+ 90 V
DD
V
REF
+ 90 V
DD
V
REF
+ 90 V
DD
mV 1
V
IL.DQ
(DC90)
DC input logic low
V
SS
V
REF
- 90 V
SS
V
REF
- 90 V
SS
V
REF
- 90
mV 1
V
IH.DQ
(AC160)
AC input logic high
V
REF
+ 160
Note 2----mV1,2,5
V
IL.DQ
(AC160)
AC input logic low Note 2
V
REF
- 160
----mV1,2,5
V
IH.DQ
(AC135)
AC input logic high
V
REF
+ 135
Note 2
V
REF
+ 135
Note 2 - - mV 1,2,5
V
IL.DQ
(AC135)
AC input logic low Note 2
V
REF
- 135
Note 2
V
REF
- 135
- - mV 1,2,5
V
IH.DQ
(AC130)
AC input logic high ----
V
REF
+ 130
Note 2 mV 1,2,5
V
IL.DQ
(AC130)
AC input logic low ----Note 2
V
REF
- 130
mV 1,2,5
V
REF
DQ
(DC)
Reference Voltage for DQ,
DM inputs
0.49*V
DD
0.51*V
DD
0.49*V
DD
0.51*V
DD
0.49*V
DD
0.51*V
DD
V3,4
Symbol Parameter
DDR3-800/1066 DDR3-1333/1600 DDR3-1866
Unit NOTE
Min. Max. Min. Max. Min. Max.
1.5V
V
IH.DQ
(DC100)
DC input logic high
V
REF
+ 100 V
DD
V
REF
+ 100 V
DD
V
REF
+ 100 V
DD
mV 1,5
V
IL.DQ
(DC100)
DC input logic low
V
SS
V
REF
- 100 V
SS
V
REF
- 100 V
SS
V
REF
- 100
mV 1,6
V
IH.DQ
(AC175)
AC input logic high
V
REF
+ 175
NOTE 2 - - - - mV 1,2,7
V
IL.DQ
(AC175)
AC input logic low NOTE 2
V
REF
- 175
----mV1,2,8
V
IH.DQ
(AC150)
AC input logic high
V
REF
+ 150
NOTE 2
V
REF
+ 150
NOTE 2 - - mV 1,2,7
V
IL.DQ
(AC150)
AC input logic low NOTE 2
V
REF
- 150
NOTE 2
V
REF
- 150
- - mV 1,2,8
V
IH.DQ
(AC135)
AC input logic high
V
REF
+ 135
NOTE 2
V
REF
+ 135
NOTE 2
V
REF
+ 135
NOTE 2 mV 1,2,7,10
V
IL.DQ
(AC135)
AC input logic low NOTE 2
V
REF
- 135
NOTE 2
V
REF
- 135
NOTE 2
V
REF
- 135
mV 1,2,8,10
V
REF
DQ
(DC)
Reference Voltage for DQ,
DM inputs
0.49*V
DD
0.51*V
DD
0.49*V
DD
0.51*V
DD
0.49*V
DD
0.51*V
DD
V3,4,9
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- 13 -
datasheetK4B4G1646E DDR3L SDRAM
Rev. 1.1
8.2 V
REF
Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages V
REFCA
and V
REFDQ
are illustrate in Figure 1. It shows a valid reference voltage
V
REF
(t) as a function of time. (V
REF
stands for V
REFCA
and V
REFDQ
likewise).
V
REF
(DC) is the linear average of V
REF
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirement in Table 7 on
page 11. Furthermore V
REF
(t) may temporarily deviate from V
REF
(DC) by no more than ± 1% V
DD
.
Figure 1. Illustration of V
REF
(DC) tolerance and VREF ac-noise limits
The voltage levels for setup and hold time measurements V
IH
(AC), V
IH
(DC), V
IL
(AC) and V
IL
(DC) are dependent on V
REF
.
"V
REF
" shall be understood as V
REF
(DC), as defined in Figure 1 .
This clarifies, that dc-variations of V
REF
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to
which setup and hold is measured. System timing and voltage budgets need to account for V
REF
(DC) deviations from the optimum position within the
data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
REF
ac-noise. Timing
and voltage effects due to ac-noise on V
REF
up to the specified limit (+/-1% of V
DD
) are included in DRAM timings and their associated deratings.
voltage
V
DD
V
SS
time
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- 14 -
datasheetK4B4G1646E DDR3L SDRAM
Rev. 1.1
8.3 AC & DC Logic Input Levels for Differential Signals
8.3.1 Differential signals definition
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 11 ] Differential AC & DC Input Levels
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK
use V
IH
/V
IL
(AC) of ADD/CMD and V
REFCA
; for DQS - DQS use V
IH
/V
IL
(AC) of DQs and V
REFDQ
; if a reduced ac-high or ac-low level is used for a signal group,
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK
, DQS, DQS need to be within the respective limits (V
IH
(DC) max, V
IL
(DC)min) for single-ended sig-
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undersheet Specification"
Symbol Parameter
DDR3-800/1066/1333/1600/1866
unit NOTE1.35V 1.5V
min max min max
V
IHdiff
differential input high +0.18 NOTE 3 +0.20 NOTE 3 V 1
V
ILdiff
differential input low NOTE 3 -0.18 NOTE 3 -0.20 V 1
V
IHdiff
(AC)
differential input high ac
2 x (V
IH
(AC) - V
REF
)
NOTE 3
2 x (V
IH
(AC) - V
REF
)
NOTE 3 V 2
V
ILdiff
(AC)
differential input low ac NOTE 3
2 x (V
IL
(AC) - V
REF
)
NOTE 3
2 x (V
IL
(AC) - V
REF
)
V2
0.0
tDVAC
V
IH
.DIFF.MIN
half cycle
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
time
tDVAC
V
IH
.DIFF.AC.MIN
V
IL
.DIFF.MAX
V
IL
.DIFF.AC.MAX
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- 15 -
datasheetK4B4G1646E DDR3L SDRAM
Rev. 1.1
[ Table 12 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.35V)
NOTE: Rising input signal shall become equal to or greater than VIH(ac) level and Falling input signal shall become equal to or less than VIL(ac) level.
[ Table 13 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS (1.5V)
NOTE : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VILdiff(ac)
level.
8.3.3 Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for
single-ended signals.
CK and CK
have to approximately reach V
SEH
min / V
SEL
max [approximately equal to the ac-levels { V
IH
(AC) / V
IL
(AC)} for ADD/CMD signals] in every
half-cycle.
DQS, DQSL, DQSU, DQS
, DQSL have to reach V
SEH
min / V
SEL
max [approximately the ac-levels { V
IH
(AC) / V
IL
(AC)} for DQ signals] in every half-cycle
proceeding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
IH
150(AC)/V
IL
150(AC) is used for ADD/CMD sig-
nals, then these ac-levels apply also for the single-ended signals CK and CK
.
Slew Rate [V/ns]
DDR3L-800/1066/1333/1600 DDR3L-1866
tDVAC [ps] @ |V
IH/
Ldiff
(AC)| = 320mV
tDVAC [ps] @ |V
IH/
Ldiff
(AC)| = 270mV
tDVAC [ps]
@ |VIH/Ldiff(ac)|
=270mV
tDVAC [ps]
@ |VIH/Ldiff(ac)|
=250mV
tDVAC [ps]
@ |VIH/Ldiff(ac)|
=260mV
min max min max min max min max min max
> 4.0 189 - 201 - 163 - 168 - 176 -
4.0 189 - 201 - 163 - 168 - 176 -
3.0 162 - 179 - 140 - 147 - 154 -
2.0 109 - 134 - 95 - 105 - 111 -
1.8 91 - 119 - 80 - 91 - 97 -
1.6 69 - 100 - 62 - 74 - 78 -
1.4 40 - 76 - 37 - 52 - 56 -
1.2 note - 44 - 5 - 22 - 24 -
1.0 note - note - note - note - note -
< 1.0 note - note - note - note - note -
Slew Rate [V/ns]
DDR3-800/1066/1333/1600 DDR3-1866
tDVAC [ps]
@ V
IH/Ldiff
(AC)= 350mV
tDVAC [ps]
@ V
IH/Ldiff
(AC)= 300mV
tDVAC [ ps ]
@ VIH/L diff(ac)
=270mv
(DQS - DQS#) only
(Optional)
tDVAC [ps]
@ V
IH/Ldiff
(AC)
= 270mV
tDVAC [ps]
@ V
IH/Ldiff
(AC)
=250mV(CK - CK#) only
min max min max min max min max min max
> 4.0 75 - 175 - 214 - 134 - 139 -
4.0 57 - 170 - 214 - 134 - 139 -
3.0 50 - 167 - 191 - 112 - 118 -
2.0 38 - 119 - 146 - 67 - 77 -
1.8 34 - 102 - 131 - 52 - 63 -
1.6 29 - 81 - 113 - 33 - 45 -
1.4 22-54-88- 9 -23-
1.2 note - 19 - 56 - note - note -
1.0 note - note - 11 - note - note -
< 1.0 note - note - note - note - note -
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