没有合适的资源?快使用搜索试试~ 我知道了~
首页AK4343音频接口芯片
AK4343音频接口芯片
需积分: 49 11 下载量 38 浏览量
更新于2023-05-28
评论
收藏 837KB PDF 举报
AK4343音频接口芯片数据手册,采用I2S接口通信,较适合STM32处理器实现音频应用
资源详情
资源评论
资源推荐
ASAHI KASEI
[AK4343]
MS0478-E-01 2006/10
- 1 -
GENERAL DESCRIPTION
The AK4343 is a stereo DAC with a built-in Headphone-Amplifier, Receiver-Amplifier and 1.2W output
Speaker-Amplifier. The AK4343 features analog mixing circuits and PLL that allows easy interfacing in
mobile phone and portable A/V player designs. The AK4343 is available in a 32pin QFN, utilizing less
board space than competitive offerings.
FEATURES
1. Playback Function
•
Digital De-emphasis Filter (tc=50/15
µ
s, fs=32kHz, 44.1kHz, 48kHz)
• Bass Boost
•
Soft Mute
•
Digital Volume (+12dB
∼
−
115.0dB, 0.5dB Step, Mute)
• Digital ALC (Automatic Level Control)
(+36dB ∼ −54dB, 0.375dB Step, Mute)
• Stereo Separation Emphasis
• Programmable EQ
• Stereo Line Output
- Performance: S/(N+D): 88dB, S/N: 92dB
• Mono Receiver-Amp
- BTL Output
- Output Power: 30mW@32Ω (AVDD=3.3V)
• Stereo Headphone-Amp
- S/(N+D): 70dB@7.5mW, S/N: 90dB
- Output Power: 70mW@16Ω (HVDD=5V), 62mW@16Ω (HVDD=3.3V)
- Pop Noise Free at Power ON/OFF
• Mono Speaker-Amp
- S/(N+D): 50dB@240mW, S/N: 90dB
- BTL Output
- Availbable for both Dynamic and Piezo Speaker
- Output Power: 1.2W@8Ω (HVDD=5V), 400mW@8Ω (HVDD=3.3V)
3.0Vrms@50Ω (HVDD=5V)
• Analog Mixing:
- 3 Stereo Input
- Gain Amplifier (+32dB/+26dB/+20dB or 0dB)
2. Power Management
3. Master Clock:
(1) PLL Mode
• Frequencies:
11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 27MHz (MCKI pin)
1fs (LRCK pin)
32fs or 64fs (BICK pin)
(2) External Clock Mode
• Frequencies: 256fs, 512fs or 1024fs (MCKI pin)
4. Output Master Clock Frequencies: 32fs/64fs/128fs/256fs
5. Sampling Rate:
• PLL Slave Mode (LRCK pin): 7.35kHz ∼ 48kHz
•
PLL Slave Mode (BICK pin): 7.35kHz
∼
48kHz
• PLL Slave Mode (MCKI pin):
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
•
PLL Master Mode:
8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz
Stereo DAC with HP/RCV/SPK-AMP
AK4343
ASAHI KASEI
[AK4343]
MS0478-E-01 2006/10
- 2 -
• EXT Master/Slave Mode:
7.35kHz ∼ 48kHz (256fs), 7.35kHz ∼ 26kHz (512fs), 7.35kHz ∼ 13kHz (1024fs)
6.
µ
P I/F: 3-wire Serial, I
2
C Bus (Ver 1.0, 400kHz High Speed Mode)
7. Master/Slave mode
8. Audio Interface Format: MSB First, 2’s complement
• 16bit MSB justified, 16bit LSB justified, 16-24bit I
2
S, DSP Mode
9. Ta = −30 ∼ 85°C (SPK-Amp=OFF)
−
30
∼
70
°
C (SPK-Amp=ON)
10. Power Supply:
• AVDD, DVDD: 2.6 ∼ 3.6V (typ. 3.3V)
•
HVDD: 2.6 ∼ 5.25V (typ. 3.3V/5.0V)
11. Package: 32pin QFN (5mm x 5mm, 0.5mm pitch)
12. Pin/Register Compatible with AK4642EN
Block Diagram
Gain-Amp
PMMICL
PMMICR
Audio
I/F
D/A
DATT
SMUTE
PMDAC
PMHPL
PMHPR
Line In
Stereo Line Out
or
Mono Receiver
Headphone
PMSPK
Speaker
Bass
Boost
PLL
PMPLL
Control
Register
LIN1
RIN1
LIN2
RIN2
HPL
HPR
MUTET
SPP
SPN
HVDD HVSS
A
VDD AVSS VCOM DVDD
CSN
PDN
CCLK
CDTI
BICK
LRCK
SDTI
MCKO
MCKI
VCOC
PMLO
LOUT/RCP
ROUT/RCN
ALC
DVSS
Stereo
Separation
HPF
I2C
LIN3/MIN
RIN3/VCOC
PMAINR2
PMAINL2
PMAINR3
PMAINL3
Figure 1. Block Diagram
ASAHI KASEI
[AK4343]
MS0478-E-01 2006/10
- 3 -
Ordering Guide
AK4343EN −30 ∼ +85°C 32pin QFN (0.5mm pitch)
AKD4343 Evaluation board for AK4343
Pin Layout
MUTET
ROUT / RCN
LOUT / RCP
MIN / LIN3
RIN2 / IN2
−
LIN2 / IN2+
LIN1 / IN1−
RIN1 / IN1+
HPL
HPR
HVSS
HVDD
SPP
SPN
MCKO
MCKI
TEST1
VCOM
A
VSS
A
VDD
VCOC / RIN3
I2C
PDN
CSN / CAD0
DVSS
DVDD
BICK
LRCK
TEST2
SDTI
CDTI / SDA
CCLK / SCL
AK4343EN
Top View
25
26
27
28
29
30
31
32
24
23
22
1
16
15
14
13
12
11
10
9
21
20
19
18
17
2
3
4
5
6
7
8
Compatibility with AK4642EN
1. Function
Function AK4642EN AK4343
SPK-Amp Max Output Power 400mW@3.3V 1.2W@5V
HP-Amp Max Output Power 62mW@3.3V 70mW@5V
Receiver-Amp No Yes
Analog Mixing for Playback 1 Mono 3 Stereo
ADC Yes No
ALC Recovery Waiting Period
128/fs ∼ 1024/fs 128/fs ∼ 16384/fs
ALC Fast Recovery Speed 4 times 4, 8 or 16 times
DSP Format No Yes
EXT Master Mode No Yes
DAC Group Delay 22/fs 25/fs
ASAHI KASEI
[AK4343]
MS0478-E-01 2006/10
- 4 -
2. Pin
Pin# AK4642EN AK4343
1 MPWR TEST1
5 VCOC VCOC/RIN3
12 SDTO TEST2
26 ROUT ROUT/RCN
27 LOUT LOUT/RCP
28 MIN MIN/LIN3
3. Register
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Power Management 1 0
PMVCM
PMMIN PMSPK PMLO PMDAC 0 PMADL
01H Power Management 2 0 HPMTN PMHPL PMHPR M/S 0 MCKO PMPLL
02H Signal Select 1 SPPSN MINS DACS DACL 0 PMMP 0
MGAIN0
03H Signal Select 2 LOVL LOPS
MGAIN1
SPKG1 SPKG0 MINL 0 0
04H Mode Control 1 PLL3 PLL2 PLL1 PLL0 BCKO 0 DIF1 DIF0
05H Mode Control 2 PS1 PS0 FS3 MSBS BCKP FS2 FS1 FS0
06H Timer Select DVTM WTM2 ZTM1 ZTM0 WTM1 WTM0 RFST1 RFST0
07H ALC Mode Control 1 0 0 ALC ZELMN LMAT1 LMAT0 RGAIN0 LMTH0
08H ALC Mode Control 2 REF7 REF6 REF5 REF4 REF3 REF2 REF1 REF0
09H Lch Input Volume Control AVL7 AVL6 AVL5 AVL4 AVL3 AVL2 AVL1 AVL0
0AH Lch Digital Volume Control DVL7 DVL6 DVL5 DVL4 DVL3 DVL2 DVL1 DVL0
0BH ALC Mode Control 3 RGAIN1 LMTH1 0 0 0 0 VBAT 0
0CH Rch Input Volume Control AVR7 AVR6 AVR5 AVR4 AVR3 AVR2 AVR1 AVR0
0DH Rch Digital Volume Control DVR7 DVR6 DVR5 DVR4 DVR3 DVR2 DVR1 DVR0
0EH Mode Control 3 0 LOOP SMUTE DVOLC BST1 BST0 DEM1 DEM0
0FH Mode Control 4 0 0 0 0 AVOLC HPM MINH DACH
10H Power Management 3 INR1 INL1 HPG MDIF2 MDIF1 INR0 INL0 PMADR
11H Digital Filter Select GN1 GN0 0 FIL1 EQ FIL3 0 0
12H FIL3 Co-efficient 0 F3A7 F3A6 F3A5 F3A4 F3A3 F3A2 F3A1 F3A0
13H FIL3 Co-efficient 1 F3AS 0 F3A13 F3A12 F3A11 F3A10 F3A9 F3A8
14H FIL3 Co-efficient 2 F3B7 F3B6 F3B5 F3B4 F3B3 F3B2 F3B1 F3B0
15H FIL3 Co-efficient 3 0 0 F3B13 F3B12 F3B11 F3B10 F3B9 F3B8
16H EQ Co-efficient 0 EQA7 EQA6 EQA5 EQA4 EQA3 EQA2 EQA1 EQA0
17H EQ Co-efficient 1 EQA15 EQA14 EQA13 EQA12 EQA11 EQA10 EQA9 EQA8
18H EQ Co-efficient 2 EQB7 EQB6 EQB5 EQB4 EQB3 EQB2 EQB1 EQB0
19H EQ Co-efficient 3 0 0 EQB13 EQB12 EQB11 EQB10 EQB9 EQB8
1AH EQ Co-efficient 4 EQC7 EQC6 EQC5 EQC4 EQC3 EQC2 EQC1 EQC0
1BH EQ Co-efficient 5 EQC15 EQC14 EQC13 EQC12 EQC11 EQC10 EQC9 EQC8
1CH FIL1 Co-efficient 0 F1A7 F1A6 F1A5 F1A4 F1A3 F1A2 F1A1 F1A0
1DH FIL1 Co-efficient 1 F1AS 0 F1A13 F1A12 F1A11 F1A10 F1A9 F1A8
1EH FIL1 Co-efficient 2 F1B7 F1B6 F1B5 F1B4 F1B3 F1B2 F1B1 F1B0
1FH FIL1 Co-efficient 3 0 0 F1B13 F1B12 F1B11 F1B10 F1B9 F1B8
20H Power Management 4 0 0
PMAINR3 PMAINL3 PMAINR2 PMAINL2 PMMICR PMMICL
21H Mode Control 5 0 0 MICR3 MICL3 0 0 AIN3 RCV
22H Lineout Mixing Select 0 0 0 0 RINR3 LINL3 RINR2 LINL2
23H HP Mixing Select 0 0 0 0 RINH3 LINH3 RINH2 LINH2
24H SPK Mixing Select 0 0 0 0 RINS3 LINS3 RINS2 LINS2
These bits are added in the AK4343.
These bits are removed from the AK4343.
ASAHI KASEI
[AK4343]
MS0478-E-01 2006/10
- 5 -
PIN/FUNCTION
No. Pin Name I/O Function
1
TEST1 -
Test 1 Pin
This pin should be left floating.
2 VCOM O
Common Voltage Output Pin, 0.45 x AVDD
Bias voltage of DAC outputs.
3 AVSS - Analog Ground Pin
4 AVDD - Analog Power Supply Pin
VCOC
O
Output Pin for Loop Filter of PLL Circuit (AIN3 bit = “0”: PLL is available)
This pin should be connected to AVSS with one resistor and capacitor in series.
5
RIN3 I Rch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)
6 I2C I
Control Mode Select Pin
“H”: I
2
C Bus, “L”: 3-wire Serial
7 PDN I
Power-Down Mode Pin
“H”: Power-up, “L”: Power-down, reset and initializes the control register.
CSN I Chip Select Pin (I2C pin = “L”: 3-wire Serial Mode)
8
CAD0 I Chip Address 1 Select Pin (I2C pin = “H”: I
2
C Bus Mode)
CCLK I Control Data Clock Pin (I2C pin = “L”: 3-wire Serial Mode)
9
SCL I Control Data Clock Pin (I2C pin = “H”: I
2
C Bus Mode)
CDTI I Control Data Input Pin (I2C pin = “L”: 3-wire Serial Mode)
10
SDA I/O Control Data Input Pin (I2C pin = “H”: I
2
C Bus Mode)
11 SDTI I Audio Serial Data Input Pin
12
TEST2 -
Test 2 Pin
This pin should be left floating.
13 LRCK I/O Input / Output Channel Clock Pin
14 BICK I/O Audio Serial Data Clock Pin
15 DVDD - Digital Power Supply Pin
16 DVSS - Digital Ground Pin
17 MCKI I External Master Clock Input Pin
18 MCKO O Master Clock Output Pin
19 SPN O Speaker Amp Negative Output Pin
20 SPP O Speaker Amp Positive Output Pin
21 HVDD - Headphone & Speaker Amp Power Supply Pin
22 HVSS - Headphone & Speaker Amp Ground Pin
23 HPR O Rch Headphone-Amp Output Pin
24 HPL O Lch Headphone-Amp Output Pin
25 MUTET O
Mute Time Constant Control Pin
Connected to HVSS pin with a capacitor for mute time constant.
ROUT O Rch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)
26
RCN O Receiver-Amp Negative Output Pin (RCV bit = “1”: BTL output)
LOUT O Lch Stereo Line Output Pin (RCV bit = “0”: Single-ended Stereo Output)
27
RCP O Receiver-Amp Positive Output Pin (RCV bit = “1”: BTL output)
MIN I Mono Signal Input Pin (AIN3 bit = “0”: PLL is available)
28
LIN3 I Lch Analog Input 3 Pin (AIN3 bit = “1”: PLL is not available)
RIN2 I Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
29
IN2−
I Rch Negative Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
LIN2 I Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
30
IN2+ I Rch Positive Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
LIN1 I Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
31
IN1−
I Lch Negative Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
RIN1 I Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
32
IN1+ I Lch Positive Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
Note 1. All input pins except analog input pins (MIN/LIN3, LIN1, RIN1, LIN2, RIN2, RIN3) should not be left floating.
Note 2. AVDD or AVSS voltage should be input to I2C pin.
剩余97页未读,继续阅读
adams8432
- 粉丝: 1
- 资源: 9
上传资源 快速赚钱
- 我的内容管理 收起
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
会员权益专享
最新资源
- c++校园超市商品信息管理系统课程设计说明书(含源代码) (2).pdf
- 建筑供配电系统相关课件.pptx
- 企业管理规章制度及管理模式.doc
- vb打开摄像头.doc
- 云计算-可信计算中认证协议改进方案.pdf
- [详细完整版]单片机编程4.ppt
- c语言常用算法.pdf
- c++经典程序代码大全.pdf
- 单片机数字时钟资料.doc
- 11项目管理前沿1.0.pptx
- 基于ssm的“魅力”繁峙宣传网站的设计与实现论文.doc
- 智慧交通综合解决方案.pptx
- 建筑防潮设计-PowerPointPresentati.pptx
- SPC统计过程控制程序.pptx
- SPC统计方法基础知识.pptx
- MW全能培训汽轮机调节保安系统PPT教学课件.pptx
资源上传下载、课程学习等过程中有任何疑问或建议,欢迎提出宝贵意见哦~我们会及时处理!
点击此处反馈
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功
评论0