Verilog实现的数字系统测试与可测性设计

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"《Digital System Test and Testable Design》由Zainalabedin Navabi撰写，专注于数字系统的测试和可测性设计，结合了高级设计语言（如Verilog HDL）来阐述测试策略和方法。本书通过使用Verilog模型和测试平台实现和解释故障仿真及测试生成算法，同时探讨了各种扫描和BIST（内置自测试）技术，并利用Verilog测试平台作为虚拟测试器来评估这些可测性方法。书中还强调在设计可测性电路时，如何运用Verilog测试平台评估并提升设计的可测性。" 该书深入介绍了数字系统测试的关键概念和技术，旨在将测试与数字设计实践相结合。测试是确保数字电路功能正确性和可靠性的关键步骤，而可测性设计则是在设计阶段就考虑测试性，从而简化后期的故障检测和调试。Verilog HDL作为一种广泛使用的硬件描述语言，被用来构建电路模型和测试平台，使得测试过程更加直观和高效。在书中，作者讲解了如何利用已有的RTL（寄存器传输层）设计和验证方法来测试数字电路，这种方法能够提高测试覆盖率，降低测试成本。故障模拟是测试生成的核心，通过Verilog模型进行故障模拟，可以预测电路在不同故障情况下的行为，帮助设计者优化测试向量。 BIST技术是现代电子系统中的一个重要组成部分，它允许电路自我检测和修复。书中详细阐述了不同类型的扫描结构（如线扫描、LFSR扫描等）以及BIST策略，这些方法可以提高测试效率，减少外部测试设备的需求。通过Verilog测试平台作为虚拟测试器，读者可以模拟实际测试环境，对这些可测性方法的效果进行评估。此外，本书还涵盖了设计可测性电路的实践，强调在设计初期就要考虑到测试需求。通过Verilog测试平台的反馈，设计者可以不断调整和改进设计，以增强其可测性，从而更有效地定位和解决潜在问题。《Digital System Test and Testable Design》是一本综合性的教材，适合电子工程和计算机科学的学生，以及从事数字系统设计和测试的专业人士学习参考。通过阅读本书，读者将获得关于数字系统测试和可测性设计的深入理解，并掌握利用现代设计工具和方法进行有效测试的技能。

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xvContents

7.5 RT Level Scan Design .............................................................................................. 253

7.5.1 RTL Design Full Scan .................................................................................. 253

7.5.2 RTL Design Multiple Scan ........................................................................... 254

7.5.3 Scan Designs for RTL .................................................................................. 258

7.6 Summary .................................................................................................................. 258

References .......................................................................................................................... 259

8 Standard IEEE Test Access Methods ............................................................................. 261

8.1 Boundary Scan Basics .............................................................................................. 261

8.2 Boundary Scan Architecture .................................................................................... 262

8.2.1 Test Access Port ........................................................................................... 262

8.2.2 Boundary Scan Registers .............................................................................. 263

8.2.3 TAP Controller ............................................................................................. 267

8.2.4 The Decoder Unit ......................................................................................... 271

8.2.5 Select and Other Units .................................................................................. 271

8.3 Boundary Scan Test Instructions .............................................................................. 271

8.3.1 Mandatory Instructions................................................................................. 272

8.4 Board Level Scan Chain Structure ........................................................................... 277

8.4.1 One Serial Scan Chain .................................................................................. 278

8.4.2 Multiple-Scan Chain with One Control Test Port ........................................ 278

8.4.3 Multiple-Scan Chains with One TDI, TDO but Multiple TMS ................... 279

8.4.4 Multiple-Scan Chain, Multiple Access Port ................................................. 279

8.5 RT Level Boundary Scan .......................................................................................... 281

8.5.1 Inserting Boundary Scan Test Hardware for CUT ....................................... 281

8.5.2 Two Module Test Case ................................................................................. 283

8.5.3 Virtual Boundary Scan Tester ....................................................................... 285

8.6 Boundary Scan Description Language ..................................................................... 290

8.7 Summary .................................................................................................................. 292

References .......................................................................................................................... 294

9 Logic Built-in Self-test ..................................................................................................... 295

9.1 BIST Basics .............................................................................................................. 295

9.1.1 Memory-based BIST .................................................................................... 295

9.1.2 BIST Effectiveness ....................................................................................... 297

9.1.3 BIST Types ................................................................................................... 297

9.1.4 Designing a BIST ......................................................................................... 298

9.2 Test Pattern Generation ............................................................................................ 300

9.2.1 Engaging TPGs............................................................................................. 300

9.2.2 Exhaustive Counters ..................................................................................... 300

9.2.3 Ring Counters ............................................................................................... 301

9.2.4 Twisted Ring Counter ................................................................................... 302

9.2.5 Linear Feedback Shift Register .................................................................... 303

9.3 Output Response Analysis ....................................................................................... 312

9.3.1 Engaging ORAs ............................................................................................ 312

9.3.2 One’s Counter ............................................................................................... 312

9.3.3 Transition Counter ........................................................................................ 314

9.3.4 Parity Checking ............................................................................................ 316

9.3.5 Serial LFSRs (SISR) .................................................................................... 316

9.3.6 Parallel Signature Analysis .......................................................................... 317

xvi Contents

9.4 BIST Architectures ................................................................................................. 319

9.4.1 BIST-related Terminologies ..................................................................... 319

9.4.2 A Centralized and Separate Board-level BIST

Architecture (CSBL) ................................................................................ 320

9.4.3 Built-in Evaluation and Self-test (BEST) ................................................. 321

9.4.4 Random Test Socket (RTS) ...................................................................... 322

9.4.5 LSSD On-chip Self Test ........................................................................... 324

9.4.6 Self-testing Using MISR and SRSG ........................................................ 325

9.4.7 Concurrent BIST ...................................................................................... 326

9.4.8 BILBO ...................................................................................................... 328

9.4.9 Enhancing Coverage ................................................................................. 329

9.5 RT Level BIST Design............................................................................................ 329

9.5.1 CUT Design, Simulation, and Synthesis .................................................. 330

9.5.2 RTS BIST Insertion .................................................................................. 330

9.5.3 Conﬁguring the RTS BIST ....................................................................... 326

9.5.4 Incorporating Conﬁgurations in BIST ...................................................... 338

9.5.5 Design of STUMPS .................................................................................. 340

9.5.6 RTS and STUMPS Results ....................................................................... 343

9.6 Summary ................................................................................................................. 343

References .......................................................................................................................... 343

10 Test Compression ............................................................................................................. 345

10.1 Test Data Compression ........................................................................................... 348

10.2 Compression Methods ............................................................................................ 347

10.2.1 Code-based Schemes ................................................................................ 347

10.2.2 Scan-based Schemes................................................................................. 357

10.3 Decompression Methods ........................................................................................ 362

10.3.1 Decompression Unit Architecture ............................................................ 363

10.3.2 Cyclical Scan Chain ................................................................................. 365

10.3.3 Code-based Decompression ..................................................................... 366

10.3.4 Scan-based Decompression ...................................................................... 372

10.4 Summary ................................................................................................................. 372

References .......................................................................................................................... 372

11 Memory Testing by Means of Memory BIST ................................................................ 375

11.1 Memory Testing ...................................................................................................... 375

11.2 Memory Structure ................................................................................................... 376

11.3 Memory Fault Model .............................................................................................. 377

11.3.1 Stuck-At Faults ......................................................................................... 377

11.3.2 Transition Faults ....................................................................................... 378

11.3.3 Coupling Faults ........................................................................................ 378

11.3.4 Bridging and State CFs ............................................................................ 378

11.4 Functional Test Procedures ..................................................................................... 378

11.4.1 March Test Algorithms ............................................................................. 378

11.4.2 March C- Algorithm ................................................................................. 379

11.4.3 MATS+ Algorithm ................................................................................... 380

11.4.4 Other March Tests .................................................................................... 380

xix

The main focus of the book is on digital systems test and design testability. The book uses Verilog

for design, test analysis, and testability of digital systems. In the first chapter, we discuss the basics

of test and testable design while discussing the aspects of test that hardware description languages

can be used for. This part discusses the entire digital system testing in terms of test methods, test-

ability methods, and testing methods, and it discusses the use of HDLs in each aspect. After the

introductory parts, we have included a chapter on the basics of Verilog and using this language for

design and test. The body of the book assumes this basic Verilog-based RT-level design knowledge

and builds test and simulation concepts upon that.

Starting in Chap. 3, the focus of the book turns to test issues, such as fault collapsing, fault simu-

lation, and test generation. This part that is regarded as covering “test methods” has four chapters

that start with the presentation of fault models, followed by fault simulation methods, and then two

chapters on test generation, discussing random HDL-based test generation and deterministic test.

For such applications, we use Verilog gate models and PLI-based testbenches that are capable of

injecting faults and performing fault simulation and test generation. In this part, Verilog testbenches

act as test programs for managing the structural model of a circuit for performing fault simulation,

calculating fault coverage, and test pattern generation.

The testability part of the book begins in Chap. 7. There are four chapters in this part (Chaps.

7–10) in which various testability methods, built-in self-test architectures, and test compression

methods are discussed. We use Verilog coding for describing the hardware of various testability

methods and BIST architectures. Verilog testbenches, in this part, act as virtual testers examining

testability and test hardware embedded in a design. Together, PLI-based fault simulation and test

generation Verilog environments of Chaps. 3–6, and Verilog coding of testability hardware provide

a complete environment for testability and BIST evaluation. Design and refinement of test hardware

can be achieved after such evaluations. This part also discusses IEEE standards for boundary scan

and core testing, and uses Verilog for describing these standards and using them in designs. The last

chapter is on memory testing with a focus on MBIST that we describe in Verilog.

Chapters

Basics of Test and Role of HDLs

Basics of test are covered in this chapter. We talk about the importance of digital system testing and

define various test terminologies. Economy of test is discussed and reducing test time by means of

better test methods, more testable designs, and more efficient testing is discussed. Relation between

design and test are discussed in this chapter.

Introduction

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