没有合适的资源?快使用搜索试试~ 我知道了~
首页ST cortex-A9 双核 MCU资料
ST cortex-A9 双核 MCU资料
![](https://csdnimg.cn/release/wenkucmsfe/public/img/star.98a08eaa.png)
MCU 也双核, cortext-A9 dual core, 600MHz.
资源详情
资源推荐
![](https://csdnimg.cn/release/download_crawler_static/2700349/bg1.jpg)
Data brief
For further information contact your local STMicroelectronics sales office.
August 2010 Doc ID 17528 Rev 3 1/34
1
SPEAr1310
Dual-core Cortex A9 embedded MPU for communications
Features
■ CPU subsystem:
– 2x ARM Cortex A9 cores, up to 600 MHz
– Supporting both symmetric (SMP) and
asymmetric (AMP) multiprocessing
– 32+32 KB L1 Instructions/Data cache per
core with parity check
– Shared 512 KB L2 cache (ECC protected)
with parity check
■ Bus: 64-bit multilayer network-on-chip
■ Memories:
– 32 KB BootROM
– 32 KB internal SRAM
– Multi-port controller (MPMC) for external
DDR2-800/DDR3-1066 with 16/32 bits
datapath, up to 1GB addressable with ECC
option for SEC/DED
– Controller (FSMC) for external NAND
Flash, parallel NOR Flash and
asynchronous SRAM
– Controller (SMI) for external serial NOR
flash
■ Connectivity:
– 2x Giga/Fast Ethernet ports (for external
GMII/RGMII/MII PHY)
– 3x Fast Ethernet (for external SMII/RMII
PHY)
– 3x PCIe 2.0 links (embedded PHY)
– 2x SATA gen-2 host port (alternative to two
PCIe)
– 1x 32-bit PCI expansion bus (up to 66 MHz)
– 2x USB 2.0 host ports with integrated
PHYs
– 1x USB2.0 OTG port with integrated PHY
– 2x CAN 2.0 a/b interfaces
– 2x TDM/E1 HDLC controllers with 256/32
time slots per frame respectively
– 2x HDLC controllers for external RS485
PHYs
– 2x I2S ports for external audio/modem
– 6x UARTs (up to 5 Mbaud)
– 1x SSP port (SPI and other protocols),
master/slave, up to 41 Mbps
– 2x I2C ports master/slave
■ Integrated support for external peripherals:
– TFT LCD controller, up to 1920 x 1200 (60
Hz), 24 bpp
– Touchscreen I/F (4-wire resistive)
– 9 x 9 keyboard controller
– Memory card interface (MCIF) supporting
SD/SDIO 2.0, SDHC, MMC 4.2/4.3,
CF/CF+ Rev 4.1, XD
■ Expansion interface (EXPI)
■ Security: C3 cryptographic accelerator
■ 13x timers and 1x real time clock
■ Miscellaneous functions:
– 2x high-performance 8-channels DMA
controllers
– JPEG HW codec
– 10 bit ADC, up to 1 Msps, 8 inputs with
autoscan capability
– Programmable bidirectional GPIO signals
with interrupt capability
– 510 + 209 one time programmable (OTP)
bits
– Embedded sensor for junction temperature
monitoring
– JTAG-PTM (debugging and test interface)
■ Power saving features:
– Power islands for leakage reduction
– IP clock gating for dynamic power reduction
– Dynamic frequency scaling
PBGA (23 x 23 mm)
www.st.com
![](https://csdnimg.cn/release/download_crawler_static/2700349/bg2.jpg)
Contents SPEAr1310
2/34 Doc ID 17528 Rev 3
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Clock and reset system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 BUSMATRIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.1 BootROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.2 Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.3 Multiport memory controller (MPMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4.4 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . 10
3.4.5 Serial memory interface (SMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5 Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.1 Giga/Fast Ethernet MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5.2 PCIe/SATA interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.3 PCI express (PCIe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.4 SATA gen-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.5 32-bit PCI expansion bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.6 USB host controllers (UHC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5.7 USB OTG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.8 Controller area network interfaces (CAN) . . . . . . . . . . . . . . . . . . . . . . . 17
3.5.9 TDM/E1 HDLC controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.10 RS485 HDLC controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.11 I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.12 Universal asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . . 20
3.5.13 Synchronous Serial Port (SSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.14 I2C controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6 Integrated support for other external peripherals . . . . . . . . . . . . . . . . . . . 22
3.6.1 TFT LCD controller (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.2 Keyboard controller (KBD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6.3 Memory card interface (MCIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Expansion interface (EXPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
![](https://csdnimg.cn/release/download_crawler_static/2700349/bg3.jpg)
SPEAr1310 Contents
Doc ID 17528 Rev 3 3/34
3.8 Security co-processor (C3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.1 General purpose timer (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.2 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10 Miscellaneous functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.1 DMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.10.2 JPEG codec (JPGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.3 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.4 General purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10.5 One-time programmable antifuse module (OTP) . . . . . . . . . . . . . . . . . . 31
3.10.6 Thermal sensing module (THSENS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.10.7 Debugging and test interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 Power management module (PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
![](https://csdnimg.cn/release/download_crawler_static/2700349/bg4.jpg)
Description SPEAr1310
4/34 Doc ID 17528 Rev 3
1 Description
The SPEAr1310 is a member of the SPEAr family of embedded MPUs for network devices.
It offers an unprecedented combination of processing performance and aggressive power
reduction control for next-generation communication appliances.
The SPEAr1310 is based on ARM's new multi-core technology (Cortex-A9 SMP/AMP) and it
is manufactured with ST's 55nm HCMOS low power silicon process.
SPEAr1310 targets cost and power sensitive networking applications for the home and
small business as well as telecom infrastructure equipment, with lowest overall leakage
under real operating conditions. The device integrates ARM's latest generation ARMv7 CPU
cores, ST's proven C3 security coprocessor, and advanced connectivity interfaces and
controllers.
Figure 1. SPEAr1310 system connectivity
Add title on master page
Add subtitle on master page
SPEAr1310
DDR2/3 RAM
Parallel
NAND/NOR
Flash
Serial
NOR
Flash
TFT Display
PCIe
Cards /
Modules
USB Peripherals
Mass
Storage
Telecom
Equipment
LCD
KBD 2x I2S
MPMC
FSMC
SMI
3x FE MAC
2x GE MAC
2x USBH
Memory
Card
Power
Supply
2x I2C
2x SATA
MCIF
3x PCIe
PCI
USB OTG
6x UART
EXPI
ADC
GPIO
FPGA
PCI Cards
USB Host or
Peripheral
2x CAN
4x HDLC
(TDM/E1/RS485)
SSP
SPI Peripherals
JTAG
LAN/WAN
Audio I/O
Test &
Debug
FE/GE
PHYs
CAN Network
Audio
Frontend
Keypad
Analog
Sources
Any device
Terminals
![](https://csdnimg.cn/release/download_crawler_static/2700349/bg5.jpg)
SPEAr1310 Description
Doc ID 17528 Rev 3 5/34
A more detailed description of the functionality is provided in the following sections of the
document.
Figure 2. SPEAr1310 functional block diagram
32 KB Boot Rom
32 KB internal SRAM
External memory controller
(MPMC) DDR2-800/DDR3-1066
up to 1GB addressable (ECC)
External NAND Flash, NOR Flash,
async SRAM interface (FSMC)
Memories
External serial Flash/EEPROM
(SMI)
8x 16-bits timers
2x DMA (8 ch.)
RTC
System IPs
Core1/Core2 (2x32KB L1
cache) up to 600 MHz
512 KB L2 cache
2x Timers & 2x watchdogs
32-bit
ARM cortex A9
1x global 64-bit timer
Power islands
Clock gating
PWR manag.
LCD
ADC autoscan
JPGC
C3 crypto
accelerator
MCIF
1x PCIe
2x PCIe/2x SATA
Specific IPs
Dual (HS-FS) USB
2.0 host
USB 2.0 OTG
2x Giga Ethernet controller
Connectivity
UART, SSP, 2x I2C , 2x I2S,
USB
PHY
USB
PHY
USB
PHY
5x UART
2x CAN
2x TDM/E1
2x RS485
GPIOs as
alternate
functions
FSMC external
memory
expansion up
to32-bit
3x Fast ethernet
controller
PCI 32-bit @66
MHz
Additional logic
EXPI
Interrupt controller
KBD
510 + 209 OTP
THSENS
6 PLLs
JTAG/test
剩余33页未读,继续阅读
![pdf](https://img-home.csdnimg.cn/images/20210720083512.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
![](https://csdnimg.cn/download_wenku/file_type_ask_c1.png)
安全验证
文档复制为VIP权益,开通VIP直接复制
![](https://csdnimg.cn/release/wenkucmsfe/public/img/green-success.6a4acb44.png)