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Rev. 2.5 June 2007
© JMicron 2006. All rights reserved. Page 1 Copying prohibited.
JMicron/JM20330
JM20330
Serial ATA Bridge Chip
Datasheet
Rev. 2.5
Rev. 2.5 June 2007
© JMicron 2006. All rights reserved. Page 2 Copying prohibited.
JMicron/JM20330
Table of Contents
0. Revision History..................................................... 3
1. General Description.................................................. 5
2. Features................................................................... 6
2.1 General................................................................ 6
2.2 Host Bridge......................................................... 6
2.3 Device Bridge...................................................... 6
3. Block Diagram........................................................ 8
3.1 Physical Layer .................................................... 8
3.2 Link Layer .......................................................... 8
3.3 Transport Layer ................................................. 9
3.4 Application Layer............................................... 9
4. Package................................................................. 10
4.1 Package Dimensions......................................... 10
4.1.1 TQFP 64 ................................................... 10
4.1.2 QFN 64 ......................................................11
4.2 Package Pin-Out............................................... 12
4.3 Pin List Table.................................................... 13
5. Pin Description..................................................... 14
5.1 Pin Type Definition........................................... 14
5.2 Serial ATA Interface......................................... 15
5.3 Parallel ATA Interface...................................... 16
5.4 Power Supply.................................................... 18
5.5 Configuration Interface ................................... 19
5.6 Parallel ATA Reverse Order............................ 21
6. Supported ATA/ATAPI Command List ............. 22
6.1 PIO Data-in Commands...................................22
6.2 PIO Data-Out Commands................................22
6.3 DMA Data-In Commands ................................23
6.4 DMA Data-Out Commands..............................23
6.5 Queued DMA Commands ................................23
6.6 PACKET/DIAG Commands ............................24
6.7 Non-Data Commands .......................................24
6.8 ATAPI PACKET Commands ...........................26
6.9 Vender Specific Command ...............................29
6.10 Ultra DMA Transfer Rate...............................33
6.11 Device Mode Master-Only Operation............34
7. UART Interface Operation..................................35
7.1 UART Interface.................................................35
7.2 SCR and Control Register Map.......................37
7.3 Register Description..........................................39
8. Electrical Characteristics.....................................43
8.1 Power Requirements.........................................43
8.2 Absolute Maximum Ratings.............................43
8.3 Typical Operation Conditions..........................43
8.4 DC Characteristics............................................44
8.5 ATA I/O DC Characteristics.............................44
8.6 ATA I/O AC Characteristics.............................44
8.7 Partial Power Consumption.............................44
8.8 Slumber Power Consumption ..........................45
9. Power-on Reset Sequence.....................................46
Rev. 2.5 June 2007
© JMicron 2006. All rights reserved. Page 3 Copying prohibited.
JMicron/JM20330
0. Revision History
Version Date Revision Description
Preliminary 2004-08-05 1. Initial B version
Preliminary 1 2004-08-27
1. Provide internal weak pull-low (Typical 31 KΩ) & internal weak pull-high (Typical 31
KΩ).
2.0 2005-01-20 1. Support Multiple-Word DMA.
2. Modify the description of signals HSTROBE and DSTROBE.
3. Modify the 6-10 Ultra DMA Transfer Rate to only support 150Mhz operation.
4. Extend the ACTL from 20 bits to 40 bits.
2.1 2005-03-10
1. Modify Absolute Maximum Ratings voltage and current.
2.2 2006-01-11
1. Add description of crystal Oscillator in page 14
2. Add industry spec. description in section 8.3
2.3 2006-07-20
1. Add power on sequence.
2. Modify Absolute Maximum Ratings voltage and current.
3. Change the minimum commercial ambient operation temperature from –10 to 0.
4. Revised REXT 12KΩ 1%
5. Add 6.11 section for device mode master-only operation.
2.4 2006-10-30
1. Add the leakage current information.
2. Rise/Fall time meets Gen2 Spec.
3. Add description about MODE[2:0] pin
4. Modify the storage temperature.
5. Remove the min absolute Junction temperature.
6. Remove the Junction temperature information.
7. Modify 8.1 Power Requirements parameter
8. Add 8.7 Partial Power Consumption parameter.
9. Add 8.8 Slumber Power Consumption parameter.
2.5 2007-06-01
1. Modify REXT resistor for both 12KΩ 1% and 12.1 KΩ 1%
Rev. 2.5 June 2007
© JMicron 2006. All rights reserved. Page 4 Copying prohibited.
JMicron/JM20330
© Copyright JMicron Technology, 2003.
All Rights Reserved.
Printed in Taiwan 2003
JMicron and the JMicron Logo are trademarks of JMicron Technology Corporation in Taiwan and/or other countries.
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT
intended for use implantation or other life supports application where malfunction may result in injury or death to persons. The
information contained in this document does not affect or change JMicron’s product specification or warranties. Nothing in this
document shall operate as an express or implied license or environments, and is presented as an illustration. The results obtained in
other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIEDE ON AN “AS IS” BASIS. In no event will JMicron be
liable for damages arising directly or indirectly from any use of the information contained in this document.
JMicron Technology Corporation
4F, No.18, Prosperity 2
nd
Road,
Science Based Industrial Park
Hsinchu, Taiwan, R.O.C
For more information on JMicron products, please visit the JMicron web site at
http://www.JMicron.com
.com or send email to sales@jmicron.com
Rev. 2.5 June 2007
© JMicron 2006. All rights reserved. Page 5 Copying prohibited.
JMicron/JM20330
1. General Description
The Serial ATA Bridge is a single chip solution for serial and parallel ATA translation. It includes the Serial ATA PHY, Link,
Transport, and parallel ATA (application layer) controller. The main applications are for legacy IDE storage devices connecting to
newer chipset supporting serial ATA, such as the iCH5 south bridge of Intel chipset, and serial ATA IDE storage devices connecting
to traditional IDE south bridge.
The Serial ATA physical, link, and transport layer are compliance to Serial ATA Generation 1, which supports a 1.5Gbps data
rate. The application layer supports both the ATA register command set and PACKET command set, which could drive both the Hard
Disk Drive and ATAPI Optical Storage such as CR-ROM, CD-RW, DVD-ROM, DVD-RW, etc. The serial ATA and application layer
support both device and host operation and could be configured by a simple HOST/DEVICE pin.
This chip is designed by 0.18um CMOS technology and 64-pin TQFP or QFN package.
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