PCIe base spec 3.0

1.3.3. Switch.................................................................................................................... 41

1.3.4. Root Complex Event Collector.............................................................................. 42

1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 42

1.5.1. Transaction Layer................................................................................................. 44

1.5.2. Data Link Layer.................................................................................................... 44

1.5.3. Physical Layer ...................................................................................................... 45

1.5.4. Layer Functions and Services............................................................................... 45

2.2.2. TLPs with Data Payloads - Rules......................................................................... 56

2.2.3. TLP Digest Rules .................................................................................................. 60

2.2.4. Routing and Addressing Rules.............................................................................. 60

2.2.5. First/Last DW Byte Enables Rules........................................................................ 64

2.2.6. Transaction Descriptor......................................................................................... 67

2.2.7. Memory, I/O, and Configuration Request Rules................................................... 72

2.2.8. Message Request Rules......................................................................................... 77

2.2.9. Completion Rules.................................................................................................. 91

2.4.3. Update Ordering and Granularity Provided by a Write Transaction................ 119

2.5.1. Virtual Channel Identification (VC ID).............................................................. 121

2.5.2. TC to VC Mapping.............................................................................................. 122

2.5.3. VC and TC Rules................................................................................................. 123

2.6.1. Flow Control Rules............................................................................................. 125

2.7.1. ECRC Rules ........................................................................................................ 136

2.7.2. Error Forwarding............................................................................................... 140

3.2.1. Data Link Control and Management State Machine Rules ................................ 148

3.3.1. Flow Control Initialization State Machine Rules ............................................... 150

3.4.1. Data Link Layer Packet Rules ............................................................................ 154

3.5.1. Introduction......................................................................................................... 159

3.5.2. LCRC, Sequence Number, and Retry Management (TLP Transmitter).............. 159

3.5.3. LCRC and Sequence Number (TLP Receiver).................................................... 171

4.2.4. Link Initialization and Training.......................................................................... 204

4.2.5. Link Training and Status State Machine (LTSSM) Descriptions........................ 219

4.2.6. Link Training and Status State Rules.................................................................. 222

4.2.7. Clock Tolerance Compensation.......................................................................... 269

4.2.8. Compliance Pattern ............................................................................................ 272

4.2.9. Modified Compliance Pattern............................................................................. 273

4.3.1. Maintaining Backwards Compatibility............................................................... 275

4.3.2. Jitter Budgeting and Measurement..................................................................... 277

4.3.7. Reference Clock Specifications........................................................................... 319

4.4.1. 8.0G Transmitter Specifications ......................................................................... 327

4.4.2. 8.0G Receiver Specifications .............................................................................. 335

4.4.3. Channel Compliance Testing.............................................................................. 345

5.5.1. Auxiliary Power Enabling................................................................................... 396

6.2.2. Error Classification............................................................................................ 404

6.2.3. Error Signaling................................................................................................... 406

6.2.4. Error Logging..................................................................................................... 413

6.2.5. Sequence of Device Error Signaling and Logging Operations .......................... 417

6.2.6. Error Message Controls ..................................................................................... 420

6.2.7. Error Listing and Rules ...................................................................................... 421