verilog 数值比较器，加法器等

verilog

数值比较器，加法器

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CS 150 - Spring 2007 - Lecture #4: Verilog - 1

Hardware Description Languages:

Verilog

! Verilog

" Structural Models

" (Combinational) Behavioral Models

" Syntax

" Examples

CS 150 - Spring 2007 - Lecture #4: Verilog - 2

Quick History of HDLs

! ISP (circa 1977) - research project at CMU

" Simulation, but no synthesis

! Abel (circa 1983) - developed by Data-I/O

" Targeted to programmable logic devices

" Not good for much more than state machines

! Verilog (circa 1985) - developed by Gateway (now Cadence)

" Similar to Pascal and C

" Delays is only interaction with simulator

" Fairly efficient and easy to write

" IEEE standard

! VHDL (circa 1987) - DoD sponsored standard

" Similar to Ada (emphasis on re-use and maintainability)

" Simulation semantics visible

" Very general but verbose

" IEEE standard

CS 150 - Spring 2007 - Lecture #4: Verilog - 3

Design Methodology

HDL

Specification

Structure and Function

(Behavior) of a Design

Simulation

Verification: Design

Behave as Required?

Functional: I/O Behavior

Logic-Level (Gates)

Transistor-Level (Electrical)

Timing: Waveform Behavior

Synthesis

Generation: Map

Specification to

Implementation

CS 150 - Spring 2007 - Lecture #4: Verilog - 4

Verilog/VHDL

! The “standard” languages

! Very similar

" Many tools provide front-ends to both

" Verilog is “simpler”

# Less syntax, fewer constructs

" VHDL supports large, complex systems

# Better support for modularization

# More grungy details

# “Hello world” is much bigger in VHDL

CS 150 - Spring 2007 - Lecture #4: Verilog - 5

Verilog

! Supports structural and behavioral descriptions

! Structural

" Explicit structure of the circuit

" How a module is composed as an interconnection of more

primitive modules/components

" E.g., each logic gate instantiated and connected to others

! Behavioral

" Program describes input/output behavior of circuit

" Many structural implementations could have same behavior

" E.g., different implementations of one Boolean function

CS 150 - Spring 2007 - Lecture #4: Verilog - 6

Verilog Introduction

! the module describes a component in the circuit

! Two ways to describe:

" Structural Verilog

# List of components and how they are connected

# Just like schematics, but using text

# Hard to write, hard to decode

# Useful if you don’t have integrated design tools

" Behavioral Verilog

# Describe

what

a component does, not

how

it does it

# Synthesized into a circuit that has this behavior

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