《ASIC与FPGA验证指南：组件建模详解》

ASIC

VERIFICATION

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CHAPTER 17 TESTBENCHES FOR COMPONENT MODELS 295

17.1 About Testbenches 295

17.1.1 Tools 295

17.2 Testbench Styles 296

17.2.1 The Empty Testbench 296

17.2.2 The Linear Testbench 296

17.2.3 The Transactor Testbench 296

17.3 Using Assertions 297

17.4 Using Transactors 298

17.5 Testing Memory Models 301

17.6 Summary 308

xiv

Contents

PREFACE

Digital electronic designs continue to evolve toward more complex, higher pincount

components operating at higher clock frequencies. This makes debugging board

designs in a lab with a logic analyzer and an oscilloscope considerably more difﬁcult

than in the past. This is because signals are becoming physically more difﬁcult to

probe and because probing them is more likely to change the operation of the circuit.

Much of the custom logic in today’s products is designed into ASICs or FPGAs.

Although this logic is usually veriﬁed through simulation as a standard part of

the design process, the interfaces to standard components on the board, such as

memories and digital signal processors, often go unsimulated and are not veriﬁed

until a prototype is built.

Waiting to test for problems this late in the design process can be expensive,

however. In terms of both time and resources, the costs are higher than perform-

ing up-front simulation. The decision not to do up-front board simulation usually

centers around a lack of models and methodology. In ASIC and FPGA Veriﬁcation:

A Guide to Component Modeling, we address both of these issues.

Historical Background

The current lack of models and methodology for board-level simulation is, in large

part, due to the fact that when digital simulation started to become popular in the

1980s, the simulators were all proprietary. Every Electronic Design Automation

(EDA) vendor had their own and it was not possible to write models that were

portable from one tool to another. They offered tools with names like HILO, SILO,

and TEGAS. Most large corporations, like IBM, had their own internal simulators.

At the ASIC and later FPGA levels each foundry had to decide which simulators

they would support. There were too many simulators available for anyone to

support them all. Each foundry had to validate that the models they provided

worked correctly on each supported release of their chosen simulators.

At the board level, the component vendors saw it was impractical to support all

the different simulators on the market. Rather than choose sides, they generally

decided not to provide models at all. This led to the EDA vendors trying to provide

models. After all, what good is a simulator if the customer has nothing to simulate?

So, each EDA vendor produced its own library of mostly the same models: 7400

series TTL, 4000 series CMOS, a few small memories, and not much else. In those

days, that might be the majority of the parts needed to complete a design. But there

were always other parts used and other models needed. Customers wanting to run

a complete simulation had to model the rest of the parts themselves.

Eventually, someone saw an opportunity to sell (or rent) component models to

all the companies that wanted to simulate their designs but did not want to create

all the models required. A company (Logic Automation) was formed to lease models

of off-the-shelf components to the groups that were designing them into new

products. They developed the technology to model the components in their own

internal proprietary format and translate them into binary code speciﬁc to each

simulator.

Verilog, VHDL, and the Origin of VITAL

Verilog started out as another proprietary simulator in 1984 and enjoyed consid-

erable success. In 1990, Cadence Design Systems placed the language in the public

domain. It became an IEEE standard in 1995.

VHDL was developed under contract to the U.S. Department of Defense. It

became an IEEE standard in 1987. Whereas Verilog is a C-like language, it is clear

that VHDL has its roots in Ada. For many years there was intense competition

between Verilog and VHDL for mind share and market share. Both languages have

their strong points. In the end, most EDA companies came out with simulators that

work with both.

Early in the language wars it was noted that Verilog had a number of built-in,

gate-level primitives. Over the years these had been optimized for performance by

Cadence and later by other Verilog vendors. Verilog also had a single deﬁned

method of reading timing into a simulation from an external ﬁle.

VHDL, on the other hand, was designed for a higher level of abstraction.

Although it could model almost anything Verilog could, and without primitives, it

allowed things to be modeled in a multitude of ways. This made performance opti-

mization or acceleration impractical. VHDL was not successfully competing with

Verilog-XL as a sign-off ASIC simulator. The EDA companies backing VHDL saw

they had to do something. The something was named VITAL, the VHDL Initiative

toward ASIC Libraries.

The VITAL Speciﬁcation

The intent of VITAL was to provide a set of standard practices for modeling ASIC

primitives, or macrocells, in VHDL and in the process make acceleration possible.

Two VHDL packages were written: a primitives package and a timing package. The

primitives package modeled all the gate-level primitives found in Verilog. Because

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Preface

MAGPR 8/18/04 2:59 PM Page xvi

these primitives were now in a standard package known to the simulator writers,

they could be optimized by the VHDL compilers for faster simulation.

The timing package provided a standard, acceleratable set of procedures for

checking timing constraints, such as setup and hold, as well as pin-to-pin propa-

gation delays. The committee writing the VITAL packages had the wisdom to avoid

reinventing the wheel. They chose the same SDF ﬁle format as Verilog for storing

and annotating timing values.

SDF is the Standard Delay Format, IEEE Standard 1497. It is a textual ﬁle format

for timing and delay information for digital electronic designs. It is used to convey

timing and delay values into both VHDL and Verilog simulations. (SDF is discussed

in greater detail in Chapter 4.)

Another stated goal of VITAL is model maintainability. It restricts the writer to

a subset of the VHDL language and demands consistant use of provided libraries.

This encourages uniformity among models, making them easily readable by anyone

familiar with VITAL. Reabability and having the difﬁcult code placed in a provided

library greatly facilitate the maintainence of models by engineers who are not the

original authors.

VITAL became IEEE Standard 1076.4 in 1995. It was reballoted in 2000. The 2000

revision offers several enhancements. These include support for multisource inter-

connect timing, fast path delay disable, and skew constraint timing checks.

However, the most important new feature is the addition of a new package to

support the modeling of static RAMs and ROMs.

The Free Model Foundry

In 1994 I was working at TRW in Redondo Beach California as a CAE manager. The

beneﬁts of board-level simulation were clear but models were not available for most

of the parts we were using. I had written models for the Hilo simulator and then

rewritten them for the ValidSim simulator and I knew I would have to write them

again for yet another simulator. I did not want to waste time writing models for

another proprietary simulator.

At this time VITAL was in its ﬁnal development and a coworker, Russ Vreeland,

convinced me to look at it. I had already tried Verilog and found it did not work

well at the board level. Although the show-stopper problems were tool related, such

as netlisting, and have since been ﬁxed, other problems remain with the language

itself. These include (but are not limited to) a lack of library support and the inabil-

ity to read the strength of a signal. My personal opinion is that Verilog is ﬁne for

RTL simulation and synthesis but a bit weak at board- and system-level modeling.

All that may be changed by SystemVerilog.

In 1994, VITAL seemed to have everything I needed to model off-the-shelf com-

ponents in a language that was supported by multiple EDA vendors. Russ ﬁgured

out how to use it for component models, developed the initial style and method-

ology, and wrote the ﬁrst models. VHDL/VITAL seemed to be the answer to our

modeling problem.

Preface xvii

MAGPR 8/18/04 2:59 PM Page xvii

But TRW was in the business of developing products, not models. We felt that

models should be supplied by the component vendors just as data sheets were. We

suggested this to a few of our suppliers and quickly realized it was going to take a

long time to convince them. In the mean time we thought we could show other

engineers how our modeling techniques worked and share models with them.

In 1995, Russ Vreeland, Luis Garcia, and I cofounded the Free Model Foundation.

Our hope was to do for simulation models what the Free Software Foundation had

done for software: promote open source standards and sharing. We incorporated as

a not-for-proﬁt. Along the way the state of California insisted that we were not a

“foundation” in their interpretation of the word. We decided we would rather switch

than ﬁght and renamed the organization the Free Model Foundry (FMF).

Today, FMF has models with timing covering over 7,000 vendor part numbers.

All are free for download from our website at www.eda.org/fmf/. The models are

generally copyrighted under the Free Software Foundation’s General Public License

(GPL). Most of the examples in this book are taken from the FMF Web site.

Structure of the Book

ASIC and FPGA Veriﬁcation: A Guide to Component Modeling is organized so that it

can be read linearly from front to back. Chapters are grouped into four parts: Intro-

duction, Resources and Standards, Modeling Basics, and Advanced Modeling. Each

part covers a number of related modeling concepts and techniques, with individ-

ual chapters building upon previous material.

Part I serves as an introduction to component models and how they ﬁt into

board-level veriﬁcation. Chapter 1 introduces the idea of board-level veriﬁcation.

It deﬁnes component models and discusses why they are needed. The concept of

technology-independent modeling is introduced, as well as how it ﬁts in the FPGA

and ASIC design ﬂow. Chapter 2 provides a guided tour of a basic component

model, including how it differs from an equivalent synthesizable model.

Part II covers the standards adhered to in component modeling and the many

supporting packages that make it practical. Chapter 3 covers several IEEE and FMF

packages that are used in writing component models. Chapter 4 provides an

overview of SDF as it applies to component modeling. Chapter 5 describes the

organization and requirements of VITAL models. Chapter 6 describes the details

of modeling delays within and between components. Chapter 7 deals with VITAL

truth tables and state tables and how to use them. In Chapter 8, the basics of

modeling timing constraints are described.

Part III puts to use the material from the earlier chapters. Chapter 9 deals with

modeling devices containing registers. Chapter 10 details the use of conditional

delays and timing constraints. Chapter 11 covers negative timing constraints.

Chapter 12 discusses the timing ﬁles and SDF backannotation that make the style

of modeling put forth here so powerful.

Part IV introduces concepts for modeling more complex components. Chapter

13 demonstrates how to use the techniques discussed to build a timing wrapper

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Preface

MAGPR 8/18/04 2:59 PM Page xviii

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《ASIC与FPGA验证指南：组件建模详解》

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