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16 List of Tables
26094 Rev. 3.30 February 2006
BIOS and Kernel Developer’s Guide for the AMD Athlon™ 64 and
AMD Opteron™ Processors
Table 30. XBAR Input Buffers .....................................................................................................143
Table 31. Default XBAR Command Buffer Allocation................................................................144
Table 32. Default Virtual Channel Command Buffer Allocation .................................................144
Table 33. An Example of a Non Default Virtual Channel Command Buffer Allocation .............145
Table 34. 2P Dual Coherent HyperTransport Command Buffer Allocation.................................145
Table 35. 8P Outer Node Virtual Channel Command Buffer Allocation .....................................146
Table 36. 8P Inner Node Virtual Channel Command Buffer Allocation......................................146
Table 37. Recommended Flow Control Buffer Allocations in UMA systems .............................147
Table 38. GART PTE Organization..............................................................................................157
Table 39. Diode Offset Encodings ................................................................................................164
Table 40. Trwt Values...................................................................................................................173
Table 41. RdPreamble Values.......................................................................................................174
Table 42. Unbuffered DIMM Support For 754-pin Lidded Micro PGA Package........................175
Table 43. Unbuffered SO-DIMM Support For 754-pin Lidless Micro PGA Package
(Single Address/Control Bus Motherboard Implementation1).....................................177
Table 44. Unbuffered SO-DIMM Support For 754-pin Lidless Micro PGA Package
(Dual Address/Control Bus Motherboard Implementation1) .......................................178
Table 45. Unbuffered DIMM Support For 939-pin Lidded Micro PGA Package........................178
Table 46. Unbuffered DIMM Support For Revision E 939-pin Lidded Micro PGA Package .....179
Table 47. SODIMM Support For Revision E 939-pin Lidded Micro PGA Package....................182
Table 48. Registered DIMM Support for 940-pin Lidded Micro PGA Package ..........................183
Table 49. DDR400 and Quad Rank Registered DIMM Support for 940-pin Lidded Micro
PGA Package ................................................................................................................184
Table 50. Sources of Machine Check Errors.................................................................................191
Table 51. DC Error Codes.............................................................................................................202
Table 52. DC Error Status Bit Settings .........................................................................................203
Table 53. Valid MC0_ADDR Bits................................................................................................204
Table 54. IC Error Codes ..............................................................................................................206
Table 55. IC Error Status Bit Settings...........................................................................................206
Table 56. Valid MC1_ADDR Bits................................................................................................207
Table 57. BU Error Codes.............................................................................................................210
Table 58. BU Error Status Bit Settings .........................................................................................211
Table 59. Valid MC2_ADDR Bits................................................................................................211
Table 60. SMM Save State (Offset FE00–FFFFh) .......................................................................221
Table 61. SMM Entry State...........................................................................................................224
Table 62. SMM ASeg-Enabled Memory Types............................................................................231
Table 63. SMM TSeg-Enabled Memory Types............................................................................232
Table 64. APIC Register Summary...............................................................................................244
Table 65. Valid Combinations of ICR Fields................................................................................254
Table 66. Power Management Categories.....................................................................................261
Table 67. ACPI-State Support by System Class ...........................................................................262
Table 68. Required SMAF Code to Stop Grant Mapping.............................................................263
Table 69. Low FID Frequency Table (< 1600 MHz)....................................................................270
Table 70. High FID Frequency Table (>= 1600 MHz).................................................................270