IEEE 1596.3-1996 LVDS标准：低电压差分信号在可扩展相干接口中的高速应用
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IEEE Std 1596.3-1996 是一个重要的行业标准，由IEEE计算机协会的微处理器和微计算机标准委员会批准，于1996年3月21日发布。该标准主要关注的是可扩展相干接口（SCI）技术，这是一种旨在提供类似计算机总线服务但通过高速点对点连接实现的高速通信方式。与传统的物理总线相比，SCI采用了一种更为灵活的设计，以实现更高的数据传输速率。
在基础规格 IEEE Std 1596-1992 中，定义了差分电平编码（differential ECL signals），这种信号具有极高的传输速率，每个2纳秒可以传输16位数据，非常适合需要快速数据交换的应用场景。然而，对于一些低功耗和兼容性要求高的电路设计，如低电压CMOS、BiCMOS和GaAs器件，基础标准的信号可能不够理想。
为了解决这个问题，IEEE Std 1596.3-1996 对 IEEE Std 1596-1992 进行了扩展，引入了一种新型的低压差分信号（LVDS）。这种信号的特点是电压摆幅低至250毫伏，大大降低了功耗，只需2.5毫安的电流即可驱动100欧姆的终端电阻，这对于低电压电路设计极其友好。此外，LVDS还支持信号编码，能够适应不同宽度的数据路径，包括4位到128位，这极大地扩展了其应用范围。
LVDS信号的设计使得它能够方便地应用于多种硬件架构，特别适合于需要高性能和低功耗的系统，如高速串行通信、存储器接口和高性能计算平台。通过这些特性，LVDS标准不仅提高了数据传输的效率，也简化了系统设计，降低了系统成本，对于推动现代电子技术的发展起到了关键作用。因此，理解和掌握IEEE Std 1596.3-1996对于工程师来说，是提升技术水平和优化系统性能的重要参考。
2 Copyright © 1996 IEEE All Rights Reserved
IEEE Std 1596.3-1996 IEEE STANDARD FOR LOW-VOLTAGE
1.3 Strategies
The basic design strategies selected by this standard include the following:
Low-voltage swing. To minimize power dissipation and enable operation at very high-speed, low-swing
(400 mV maximum) signals are specified.
Differential signals. Small signal swings require differential signaling for adequate noise margin in practical
systems.
Self-terminated. To minimize board real estate and costs, and to maximize clock rates, each receiver is
assumed to provide its own termination resistors.
Uniform ground. The standard assumes that the ground potential difference between driver and receiver is
kept small by the system design. The mechanism for constraining the ground potential difference is beyond
the scope of this standard.
The most controversial decision was to use differential signals, which at first appears to double the number of signal
lines. The pin-count overhead is actually much less than this, since reliable single-ended schemes require many more
ground signals (many high-speed chips and/or backplanes provide one ground for every two signal pins) and run
significantly slower. Other design benefits associated with differential signals include the following:
Constant driver current. The transmitter consumes a (near) constant current when driving the links; the
current remains the same, but is routed in the opposite direction when the signal value changes. This
simplifies the design of power-distribution wiring.
Constant link current. The net signaling current in a differential link is (nearly) constant, which greatly
simplifies system design. The links are unidirectional and transmitters always drive a differential signal per
table 2–1 or table 2–2. Reversing or stopping links would cause the net common-mode signaling current to
change, creating system noise.
Low power. A low signal current can be used, since much of the induced noise and ground-bounce appears as
a common-mode signal.
Simple board design. Although differential signals must be carefully routed on adjacent matched tracks, they
are usually less sensitive to imperfections in the transmission line environment.
Low EMI. Differential signals minimize the area between the signal and the return path. In addition, the equal
and opposite currents create canceling electromagnetic fields. This dramatically reduces the electromagnetic
emissions.
Low susceptibility to externally generated noise. Though these links generate little noise, other parts of the
system may. Differential signals are relatively immune to this noise.
1.4 Design models
1.4.1 Source-synchronous data
The SCI-LVDS link model assumes unidirectional operation (the driver always at one end of the link, the receiver at
the other), and that a clock signal is sent along with the data as though it is just another data bit.
Both edges of the clock are used to delimit data, so the maximum transition rate of the clock is the same as the
maximum transition rate of the data signals. This clock flows through the link at the same velocity as the data, and is
to be used as the time reference for sampling the data.
In most applications, the received sampled data will need to be synchronized to the receiver’s local clock. If the
transmitter’s clock and the receiver's clock are independent, and thus perhaps at slightly different frequencies,
occasional symbols will need to be inserted or removed from time to time in an elasticity buffer in order to maintain
synchronization.
Authorized licensed use limited to: NORTHWESTERN POLYTECHNICAL UNIVERSITY. Downloaded on March 16,2023 at 09:50:02 UTC from IEEE Xplore. Restrictions apply.
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