AS3911/as3911B 高集成 NFC Initiator/HF Reader IC 手册

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AS3911/AS3911B 规格说明 AS3911/AS3911B 是一款高度集成的近距离通信（NFC）发起器/高频阅读器集成电路（IC），它包含模拟前端（AFE）和高度集成的数据帧系统，支持 ISO18092（NFCIP-1）发起器、ISO18092（NFCIP-1）活动目标、ISO14443A 和 B 阅读器（包括高速率）和 FeliCa™ 阅读器。 AS3911/AS3911B 的特点： 1. 高度集成：AS3911/AS3911B 集成了模拟前端（AFE）和高度集成的数据帧系统，能够实现 NFC 发起器和阅读器的功能。 2. 支持多种协议：AS3911/AS3911B 支持 ISO18092（NFCIP-1）发起器、ISO18092（NFCIP-1）活动目标、ISO14443A 和 B 阅读器（包括高速率）和 FeliCa™ 阅读器，能够满足不同应用场景的需求。 3. 自动天线调整技术：AS3911/AS3911B 采用了 ams 独有的自动天线调整技术，能够优化天线的性能，提高读取距离和稳定性。 4. 低功率应用：AS3911/AS3911B 包含多种功能，能够满足低功率应用的需求，包括两路差分低阻抗（1Ω）天线驱动器。 5. 高度灵活性：AS3911/AS3911B 能够实现其他标准和自定义协议的实现，通过使用 AFE 和在外部微控制器中实现帧结构（流模式和透明模式）。 6. 优化的 RF 性能：AS3911/AS3911B 的设计目标是为了实现优化的 RF 性能和灵活性，能够满足基础设施方面的需求。 7. 低功率设计：AS3911/AS3911B 的设计目标是为了实现低功率应用，能够满足低功率设备的需求。 AS3911/AS3911B 的应用场景包括： 1. 近距离通信（NFC）应用 2. 支付系统 3. 认证系统 4. 数据交换应用 5. 智能家居应用 AS3911/AS3911B 是一款高度集成、功能丰富的 NFC 发起器/高频阅读器集成电路，能够满足不同应用场景的需求，具有广泛的应用前景。

Page 16 ams Datasheet

Document Feedback [v2-10] 2014-Dec-09

AS3911 − Detailed Description

One regulator is for the analog blocks, one for digital blocks,

there is also a separate one for the antenna drivers. In case of

low cost applications some (or all) regulators may not be used

to save on external components.

This block additionally generates a reference voltage for the

analog processing (AGD - analog ground). This voltage also has

an associated external buffer capacitor.

POR and Bias

This block contains the bias current and voltage generator

which provides bias currents and reference voltages to all other

blocks. It also incorporates a Power on Reset (POR) circuit which

provides a reset at power-up and at low supply levels.

RC Oscillator and Wake-up Timer

The AS3911 includes several possibilities of low power

detection of a card presence (capacitive sensor, phase

measurement, amplitude measurement). RC oscillator and

periodic detection. When presence of a card is detected an

interrupt is sent to controller.

ISO14443 and NFCIP-1 Framing

This block performs framing for receive and transmit according

to the selected ISO mode and bit rate settings.

In reception it takes demodulated sub-carrier signal from

Receiver. It recognizes the SOF, EOF and data bits, performs

parity and CRC check, organizes the received data in bytes and

places them in the FIFO.

During transmit, it operates inversely, it takes bytes from FIFO,

generates parity and CRC bits, adds SOF and EOF and performs

final encoding before passing modulation signal to transmitter.

In Transparent mode, the framing and FIFO are bypassed, the

digitized sub-carrier signal, which is Receiver output, is directly

sent to MISO pin, signal applied to MOSI pin is directly used to

modulate the transmitter.

FIFO

The AS3911 contains a 96 byte FIFO. Depending on the mode,

it contains either data which has been received or data which

is to be transmitted.

Control Logic

The control logic contains I/O registers which define operation

of device.

ams Datasheet Page 17

[v2-10] 2014-Dec-09 Document Feedback

AS3911 − Application Information

SPI Interface

A 4-wire Serial Peripheral Interface (SPI) is used for

communication between external microcontroller and the

AS3911.

Operating Modes

The AS3911 operating mode is defined by the contents of the

Operation Control Register.

At power-up all bits of the Operation Control Register are set to

0, the AS3911 is in Power-down mode. In this mode AFE static

power consumption is minimized, only the POR and part of the

bias are active, the regulators are transparent and are not

operating. The SPI is still functional in this mode so all settings

of ISO mode definition and configuration registers can be done.

Control bit en (bit 7 of the Operation Control Register) is

controlling the quartz crystal oscillator and regulators. When

this bit is set, the device enters in Ready mode. In this mode

the quartz crystal oscillator and regulators are enabled. An

interrupt is sent to inform the microcontroller when the

oscillator frequency is stable.

Enable of Receiver and Transmitter are separated so it is

possible to operate one without switching on the other (control

bits rx_en and tx_en). In some cases this may be useful, in case

the reader field has to be maintained and there is no

transponder response expected receiver can be switched-off to

save current. Another example is NFCIP-1 active

communication receive mode in which RF field is generated by

the initiator and only Receiver operates.

Asserting the Operation Control Register bit wu while the other

bits are set to 0 puts the AS3911 into the Wake-up mode which

is used to perform low power detection of card presence. In this

mode the low power RC oscillator and register configurable

Wake-up timer are used to schedule periodic measurement(s).

When a difference to the predefined reference is detected an

interrupt is sent to wake-up the micro. Capacitive sensor, phase

measurement and amplitude measurement are available.

Transmitter

The Transmitter contains two identical push-pull driver blocks

connected to the pins RFO1 and RFO2. These drivers are

differentially driving external antenna LC tank. It is also possible

to operate only one of the two drivers by setting the IO

Configuration Register 1 bit single. Each driver is composed of

8 segments having binary weighted output resistance. The MSB

segment typical ON resistance is 2Ω, when all segments are

turned on; the output resistance is typically 1Ω. Usually all

segments are turned on to define the normal transmission

(non-modulated) level.

Application Information

Page 18 ams Datasheet

Document Feedback [v2-10] 2014-Dec-09

AS3911 − Application Information

It is also possible to switch off certain segments when driving

the non-modulated level to reduce the amplitude of signal on

the antenna and/or to reduce the antenna Q factor without

making any hardware changes. The RFO Normal Level

Definition Register defines which segments are turned on to

define the normal transmission (non-modulated) level. Default

setting is that all segments are turned on.

Using the single driver mode the number and therefore the cost

of the antenna LC tank components is halved, but also the

output power is reduced. In single mode it possible to connect

two antenna LC tanks to the two RFO outputs and multiplex

between them by controlling the IO Configuration Register 1

bit rfo2.

In order to transmit the data the transmitter output level needs

to be modulated. The AM and OOK modulation are supported.

The type of modulation is defined by setting the bit tr_am in

the Auxiliary Definition Register. For the operation modes

supported by the AS3911 framing the setting of modulation

type is done automatically by sending direct command Analog

Preset.

During the OOK modulation (for example ISO14443A) the

Transmitter drivers stop driving the carrier frequency; drivers

are frozen in state before the modulation. As consequence the

amplitude of the antenna LC tank oscillation decays, the time

constant of the decay is defined with the LC tank Q factor. The

decay time in case of OOK modulation can be shortened by

asserting the Auxiliary Definition Register bit ook_hr. When this

bit is set to logic one the drivers are put in tristate during the

OOK modulation.

AM modulation (for example ISO14443B) is done by increasing

the output driver impedance during the modulation time. This

is done by reducing the number of driver segments which are

turned on. The AM modulated level can be automatically

adjusted to the target modulation depth by defining the target

modulation depth in the AM Modulation Depth Control

command. Please refer to AM Modulation Depth: Definition and

Calibration for further details.

Slow Transmitter Ramping

When transmitter is enabled it starts to drive the antenna LC

tank with full power, the ramping of field emitted by antenna

is defined by antenna LC tank Q factor.

However there are some reader systems where the reader field

has to transition with a longer transition time when it is

enabled. The STIF (Syndicat des transports d'Ile de France)

specification requires a transition time from 10% to 90% of field

longer than or equal to 10 μs.

The AS3911 supports that feature. It is realized by collapsing

VSP_RF regulated voltage when transmitter is disabled and

ramping it when transmitter is enabled. Typical transition time

is 15 μs at 3V supply and 20 μs at 5V supply.

ams Datasheet Page 19

[v2-10] 2014-Dec-09 Document Feedback

AS3911 − Application Information

Procedure to implement the slow transition:

• When transmitter is disabled set IO Configuration Register

2 bit slow_up to 1. Keep this state at least 2 ms to allow

discharge of VSP_RF.

• Enable transmitter, its output will ramp slowly.

• Before sending any command set the bit slow_up back

to 0.

Receiver

The receiver performs demodulation of the transponder

sub-carrier modulation which is superimposed on the

13.56MHz carrier frequency. It performs AM and/or PM

demodulation, amplification, band-pass filtering and

digitalization of sub-carrier signals. Additionally it performs

RSSI measurement, automatic gain control (AGC) and Squelch

function.

In typical application the Receiver inputs RFI1 and RFI2 are

outputs of capacitor dividers connected directly to the

terminals of antenna coil. Such concept assures that the two

input signals are in phase to the voltage on antenna coil. Care

has to be taken during design of capacitive divider that the RFI1

and RFI2 input signal pp value does not exceed the VSP_A

supply voltage.

Receiver comprises two complete receive channels for AM

demodulation and PM demodulation. In case both channels are

active the selection of channel used for reception framing is

done automatically by receive framing logic. The receiver is

switched on when Operation Control Register bit rx_en is set to

one. Additionally the Operation Control Register contains bits

rx_chn and rx_man; rx_chn defines whether both, AM and PM,

demodulation channels will be active or only one of them, while

bit rx_man defines the channel selection mode in case both

channels are active (automatic or manual). Operation of the

Receiver is controlled by four Receiver Configuration registers.

The operation of the receiver is additionally controlled by the

signal rx_on which is set high when modulated signal is

expected on the receiver input. This signal is used to control

RSSI and AGC and also enables processing of receiver output

by Framing logic. Signal rx_on is automatically set high after

Mask Receive timer expires. Signal rx_on can also be directly

controlled by the controller by sending direct commands Mask

Receive Data and Unmask Receive Data. Figure 14 illustrates the

Receiver block diagram.

Demodulation Stage

First stage performs demodulation of transponder sub-carrier

response signal, which is superimposed on HF field carrier. Two

different blocks are implemented for AM demodulation: Peak

Detector and AM demodulator mixer. The choice of the

demodulator, which is used, is made by the Receiver

Configuration Register 1 bit amd_sel.

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