Corundum：100-Gbps开源网络接口卡设计

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"Corundum是一个开源的、基于FPGA的网络接口开发原型平台，支持高达100Gbps及以上的速度。它旨在提供实时、高线速率操作的能力，包括高性能数据路径、10G/25G/100G以太网MACs、PCI Express gen3接口、自定义PCIe DMA引擎以及原生的高精度IEEE 1588 PTP时间戳功能。其关键特性是可扩展的队列管理，能够支持超过10,000个队列，并结合可扩展的传输调度器，实现对包传输的细粒度硬件控制。通过与多个网络接口、每个接口的多个端口以及端口级事件驱动的传输调度相结合，这些特性使得开发高级网络接口、架构和协议成为可能。软件接口与这些硬件功能相结合，形成了一个高性能的开发环境，便于进行灵活的网络编程和优化。 Corundum平台的设计目标是推动网络研究和创新，尤其是对于那些需要高速、低延迟和精细控制的场景。使用FPGA（Field-Programmable Gate Array）作为基础，设计者可以自由定制数据路径和控制逻辑，以满足特定的网络应用需求。FPGA的优势在于其可重配置性，允许开发者快速迭代和调整设计，以适应不断变化的网络标准和技术趋势。 10G/25G/100G以太网MACs模块是Corundum的关键组件，它们负责物理层的数据传输，确保在高速网络环境下稳定、高效地处理数据流。这些MACs支持多种速度等级，可以适应不同的网络环境和连接需求。同时，PCI Express gen3接口提供了与主机系统的高速连接，确保数据在NIC和CPU之间快速移动，减少潜在的性能瓶颈。自定义PCIe DMA引擎允许数据在不占用CPU资源的情况下直接在内存和NIC之间传输，进一步降低了延迟并提高了整体系统效率。而IEEE 1588 Precision Time Protocol (PTP)时间戳功能则为网络中的时间同步提供了硬件支持，这对于许多实时和分布式系统来说至关重要。 Corundum的可扩展队列管理和传输调度器是其核心创新之一。这种设计允许为每个连接或流分配独立的队列，从而实现对网络流量的精细化管理。通过灵活的调度策略，开发者可以实现复杂的流量控制和优先级设置，以优化网络性能和响应时间。此外，多接口和多端口能力让Corundum能够处理更复杂的网络拓扑，如负载均衡和故障切换。事件驱动的传输调度则确保了网络操作的高度并发性和实时性，这在高并发的云服务和数据中心环境中尤为重要。 Corundum为网络研究人员和工程师提供了一个强大的工具，用于构建和测试下一代高速网络技术。它的开源性质促进了知识共享和社区合作，加速了网络技术的发展和创新。通过利用Corundum，开发者可以探索新的网络架构、协议和服务，以满足未来网络对带宽、延迟和可编程性的更高要求。"

Corundum: An Open-Source 100-Gbps NIC

Alex Forencich, Alex C. Snoeren, George Porter, George Papen

Department of Electrical and Computer Engineering

University of California, San Diego

{jforenci, snoeren, gmporter, gpapen}@eng.ucsd.edu

Abstract—Corundum is an open-source, FPGA-based proto-

typing platform for network interface development at up to 100

Gbps and beyond. The Corundum platform includes several core

features to enable real-time, high-line-rate operations including:

a high-performance datapath, 10G/25G/100G Ethernet MACs,

PCI Express gen 3, a custom PCIe DMA engine, and native

high-precision IEEE 1588 PTP timestamping. A key feature

is extensible queue management that can support over 10,000

queues coupled with extensible transmit schedulers, enabling

ﬁne-grained hardware control of packet transmission. In con-

junction with multiple network interfaces, multiple ports per

interface, and per-port event-driven transmit scheduling, these

features enable the development of advanced network interfaces,

architectures, and protocols. The software interface to these

hardware features is a high-performance driver for the Linux

networking stack. The platform also supports scatter/gather

DMA, checksum ofﬂoading, receive ﬂow hashing, and receive-

side scaling. Development and debugging is facilitated by a

comprehensive open-source, Python-based simulation framework

that includes the entire system from a simulation model of the

driver and PCI express interface to the Ethernet interfaces.

The power and ﬂexibility of Corundum is demonstrated by the

implementation of a microsecond-precision time-division multiple

access (TDMA) hardware scheduler to enforce a TDMA schedule

at 100 Gbps line rate with no CPU overhead.

I. INTRODUCTION AND BACKGROUND

The network interface controller (NIC) is the gateway

through which a computer interacts with the network. The

NIC forms a bridge between the software stack and the

network, and the functions of this bridge deﬁne the network

interface. Both the functions of the network interface as well

as the implementation of those functions are evolving rapidly.

These changes have been driven by the dual requirements

of increasing line rates and NIC features that support high-

performance distributed computing and virtualization. The

increasing line rates have led to many NIC functions that must

be implemented in hardware instead of software. Concurrently,

new network functions such as precise transmission control for

multiple queues are needed to implement advanced protocols

and network architectures.

To meet the need for an open development platform for

new networking protocols and architectures at realistic line

rates, we are developing an open-source

high-performance,

FPGA-based NIC prototyping platform. This platform, called

Corundum, is capable of operation up to at least 94 Gbps, is

fully open source and, along with its driver, can be used across

a complete network stack. The design is both portable and

Corundum codebase: https://github.com/ucsdsysnet/corundum

compact, supporting many different devices while also leaving

ample resources available for further customization even on

smaller devices. We show that Corundum’s modular design

and extensibility permit co-optimized hardware/software solu-

tions to develop and test advanced networking applications in

a realistic setting.

A. Motivation and previous work

The motivation for the development of Corundum can be

understood by looking at how network interface features in

existing NIC designs are currently partitioned between hard-

ware and software. Hardware NIC functions fall into two main

categories. The ﬁrst category consists of simple ofﬂoading

features that remove some per-packet processing from the

CPU—such as checksum/hash computation and segmentation

ofﬂoading that enables the network stack to process packets

in batches. The second category consists of features that must

be implemented in hardware on the NIC to achieve high

performance and fairness. These features include ﬂow steering,

rate limiting, load balancing, and time stamping.

Traditionally, the hardware functions of NICs are built into

proprietary application-speciﬁc integrated circuits (ASICs).

Coupled with economies of scale, this enables high per-

formance at low cost. However, the extensibility of these

ASICs is limited and the development cycle to add new

hardware functions can be expensive and time-consuming [1].

To overcome these limitations, a variety of smart NICs and

software NICs have been developed. Smart NICs provide

powerful programmability on the NIC, generally by providing

a number of programmable processing cores and hardware

primitives. These resources can be used to ofﬂoad various

application, networking, and virtualization operations from the

host. However, smart NICs do not necessarily scale well to

high line rates, and hardware features can be limited [1].

Software NICs offer the most ﬂexibility by implementing

network functionality in software, bypassing most of the

hardware ofﬂoading features. As a result, new functions can

be developed and tested quickly, but with various trade-offs

including consuming host CPU cycles and not necessarily

supporting operation at full line rate. Additionally, because of

the inherent random interrupt-driven nature of software, the

development of networking applications that require precise

transmission control is infeasible [2]. Despite this, many

research projects [3]–[6] have implemented novel NIC func-

tions in software by either modifying the network stack or

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