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Corundum: An Open-Source 100-Gbps NIC
Alex Forencich, Alex C. Snoeren, George Porter, George Papen
Department of Electrical and Computer Engineering
University of California, San Diego
{jforenci, snoeren, gmporter, gpapen}@eng.ucsd.edu
Abstract—Corundum is an open-source, FPGA-based proto-
typing platform for network interface development at up to 100
Gbps and beyond. The Corundum platform includes several core
features to enable real-time, high-line-rate operations including:
a high-performance datapath, 10G/25G/100G Ethernet MACs,
PCI Express gen 3, a custom PCIe DMA engine, and native
high-precision IEEE 1588 PTP timestamping. A key feature
is extensible queue management that can support over 10,000
queues coupled with extensible transmit schedulers, enabling
fine-grained hardware control of packet transmission. In con-
junction with multiple network interfaces, multiple ports per
interface, and per-port event-driven transmit scheduling, these
features enable the development of advanced network interfaces,
architectures, and protocols. The software interface to these
hardware features is a high-performance driver for the Linux
networking stack. The platform also supports scatter/gather
DMA, checksum offloading, receive flow hashing, and receive-
side scaling. Development and debugging is facilitated by a
comprehensive open-source, Python-based simulation framework
that includes the entire system from a simulation model of the
driver and PCI express interface to the Ethernet interfaces.
The power and flexibility of Corundum is demonstrated by the
implementation of a microsecond-precision time-division multiple
access (TDMA) hardware scheduler to enforce a TDMA schedule
at 100 Gbps line rate with no CPU overhead.
I. INTRODUCTION AND BACKGROUND
The network interface controller (NIC) is the gateway
through which a computer interacts with the network. The
NIC forms a bridge between the software stack and the
network, and the functions of this bridge define the network
interface. Both the functions of the network interface as well
as the implementation of those functions are evolving rapidly.
These changes have been driven by the dual requirements
of increasing line rates and NIC features that support high-
performance distributed computing and virtualization. The
increasing line rates have led to many NIC functions that must
be implemented in hardware instead of software. Concurrently,
new network functions such as precise transmission control for
multiple queues are needed to implement advanced protocols
and network architectures.
To meet the need for an open development platform for
new networking protocols and architectures at realistic line
rates, we are developing an open-source
1
high-performance,
FPGA-based NIC prototyping platform. This platform, called
Corundum, is capable of operation up to at least 94 Gbps, is
fully open source and, along with its driver, can be used across
a complete network stack. The design is both portable and
1
Corundum codebase: https://github.com/ucsdsysnet/corundum
compact, supporting many different devices while also leaving
ample resources available for further customization even on
smaller devices. We show that Corundum’s modular design
and extensibility permit co-optimized hardware/software solu-
tions to develop and test advanced networking applications in
a realistic setting.
A. Motivation and previous work
The motivation for the development of Corundum can be
understood by looking at how network interface features in
existing NIC designs are currently partitioned between hard-
ware and software. Hardware NIC functions fall into two main
categories. The first category consists of simple offloading
features that remove some per-packet processing from the
CPU—such as checksum/hash computation and segmentation
offloading that enables the network stack to process packets
in batches. The second category consists of features that must
be implemented in hardware on the NIC to achieve high
performance and fairness. These features include flow steering,
rate limiting, load balancing, and time stamping.
Traditionally, the hardware functions of NICs are built into
proprietary application-specific integrated circuits (ASICs).
Coupled with economies of scale, this enables high per-
formance at low cost. However, the extensibility of these
ASICs is limited and the development cycle to add new
hardware functions can be expensive and time-consuming [1].
To overcome these limitations, a variety of smart NICs and
software NICs have been developed. Smart NICs provide
powerful programmability on the NIC, generally by providing
a number of programmable processing cores and hardware
primitives. These resources can be used to offload various
application, networking, and virtualization operations from the
host. However, smart NICs do not necessarily scale well to
high line rates, and hardware features can be limited [1].
Software NICs offer the most flexibility by implementing
network functionality in software, bypassing most of the
hardware offloading features. As a result, new functions can
be developed and tested quickly, but with various trade-offs
including consuming host CPU cycles and not necessarily
supporting operation at full line rate. Additionally, because of
the inherent random interrupt-driven nature of software, the
development of networking applications that require precise
transmission control is infeasible [2]. Despite this, many
research projects [3]–[6] have implemented novel NIC func-
tions in software by either modifying the network stack or