提升性能与降低延迟：多处理器架构关键技术

多处理器技术

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本文档深入探讨了"Chip Multiprocessor Architecture Techniques to Improve Throughput and Latency"的主题，针对现代高性能微处理器设计中的关键挑战。多处理器架构（通常称为多核微处理器或CMPs）已经成为提升性能的主要途径，原因在于几个关键因素。首先，单核处理器的性能不再随规模扩大而线性增长，因为传统的超标量指令调度技术无法充分利用常规指令流中的并行性。随着技术的发展，单纯的时钟速度提升已经受限，因为这会导致功耗激增，除非在冷却系统支持下。其次，现代微处理器芯片上的大量晶体管使得设计和调试大型处理器的成本越来越高，每年或每两年更新一次大型处理器已经变得代价过高。因此，为了应对这些挑战，研究者们开发了各种多处理器架构技术，旨在提高吞吐量（处理能力）和降低延迟（响应时间）。 Chip Multiprocessor Architecture 技术集成了多个核心，通过并行执行任务来提升整体性能。这包括但不限于以下策略： 1. **多核设计**：通过集成多个独立但协同工作的核心，任务可以在不同的核心之间分发，实现并行计算，从而提升处理能力。 2. **超线程（Hyper-Threading）**：允许单个物理核心模拟出多个逻辑核心，通过时间片轮转，让每个核心看起来像是有两个独立的执行单元，进一步挖掘处理器潜力。 3. **流水线优化**：改进指令流水线，使其更有效地处理并行执行的指令，减少执行时间和依赖冲突。 4. **Cache一致性管理**：优化缓存策略，确保不同核心之间的数据访问协调一致，避免缓存冲突和性能瓶颈。 5. **动态频率调整**：根据工作负载变化，动态地调整核心频率，以平衡能耗与性能。 6. **非冯·诺依曼架构创新**：探索非传统架构，如向量化处理、多模态处理等，利用硬件特性提供更高的并行性和计算效率。 7. **系统级并行性**：通过软件层面的并行编程模型（如OpenMP, MPI等）来支持大规模并行任务的执行。 8. **电源管理和散热策略**：设计能有效管理能耗的系统，确保在性能提升的同时，保持在可接受的温度范围内。该文档由Kunle Olukotun, Lance Hammond, 和 James Laudon三位作者撰写，作为 Morgan & Claypool 出版社的《计算机体系结构合成讲座》系列第3卷，旨在为读者提供对多处理器架构技术的深入了解和实用指导。对于任何希望在高性能计算和现代微处理器设计中追求更高吞吐量和更低延迟的工程师和研究人员来说，这是不可或缺的参考资料。

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book Mobk089 October 26, 2007 10:22

8 CHIP MULTIPROCESSOR ARCHITECTURE

to utilize parallelism from the traditional large-grain task and process level parallelism province

of SMPs. In addition, due to the much lower communication latencies between processor cores

and their ability to incorporate new features that take advantage of these short latencies, such as

speculative thread mechanisms, CMPs can attack ﬁne-grained parallelism of loops, tasks and

even basic blocks.

1.3 A SIMPLE EXAMPLE: SUPERSCALAR VS. CMP

A good way to illustrate the inherent advantages and disadvantages of a CMP is by compar-

ing performance results obtained for a superscalar uniprocessor with results from a roughly

equivalent CMP. Of course, choosing a pair of “roughly equivalent” chips when the under-

lying architectures are so different can involve some subjective judgment. One way to deﬁne

“equivalence” is to design the two different chips so that they are about the same size (in terms

of silicon area occupied) in an identical process technology, have access to the same off-chip

I/O resources, and run at the same clock speed. With models of these two architectures, we

can then simulate code execution to see how the performance results differ across a variety of

application classes.

To give one example, we can build a CMP made up of four small, simpler processors scaled

so that they should occupy about the same amount of area as a single large, superscalar processor.

Table 1.1 shows the key characteristics that these two “equivalent” architectures would have

if they were actually built. The large superscalar microarchitecture (SS) is essentially a 6-way

superscalar version of the MIPS R10,000 processor [4], a prominent processor design from

the 1990s that contained features seen in virtually all other leading-edge, out-of-order issue

processors designed since. This is fairly comparable to one of today’s leading-edge, out-of-order

superscalar processors. The chip multiprocessor microarchitecture (CMP), by contrast, is a 4-

way CMP composed of four identical 2-way superscalar processors similar to early, in-order

superscalar processors from around 1992, such as the original Intel Pentium and DEC Alpha.

In both architectures, we model the integer and ﬂoating point functional unit result and repeat

latencies to be the same as those in the real R10,000.

Since the late 1990s, leading-edge superscalar processors have generally been able to

issue about 4–6 instructions per cycle, so our “generic” 6-way issue superscalar architecture is

very representative of, or perhaps even slightly more aggressive than, today’s most important

desktop and server processors such as the Intel Core and AMD Opteron series processors.

As the ﬂoorplan in Fig. 1.5 indicates, the logic necessary for out-of-order instruction issue

and scheduling would dominate the area of the chip, due to the quadratic area impact of

supporting very wide instruction issue. Altogether, the logic necessary to handle out-of-order

instruction issue occupies about 30% of the die for a processor at this level of complexity. The

on-chip memory hierarchy is similar to that used by almost all uniprocessor designs—a small,

book Mobk089 October 26, 2007 10:22

10 CHIP MULTIPROCESSOR ARCHITECTURE

External

Interface

Instruction

Fetch

Instruction

Cache

(32 KB)

Data

Cache

(32 KB)

TLB

Inst. Decode &

Rename

Reorder Buffer,

Instruction Queues,

and Out-of-Order Logic

Floating Point

Unit

Integer Unit

On-Chip L2 Ca h

ce2(56KB)

Clo kc ing & aPds

21 mm

FIGURE 1.5: Floorplan for the 6-issue dynamic superscalar microprocessor.

uniﬁed 256 KB L2 cache that takes four cycles to access, which is smaller but faster than most

L2 caches in typical processors from industry today.

In contrast, the CMP architecture is made up of four 2-way superscalar processors

interconnected by a crossbar that allows the processors to share the L2 cache. On the die, the

four processors are arranged in a grid with the L2 cache at one end, as shown in Fig. 1.6. The

number of execution units actually increases in the CMP scenario because the 6-way processor

included three units of each type, while the 4-way CMP must have four—one for each core.

On the other hand, the issue logic becomes dramatically smaller, due to the decrease in the

number of instruction buffer ports and the smaller number of entries in each instruction buffer.

The scaling factors of these two units balance each other out, leaving the entire 4 × 2-way

CMP very close to one-fourth of the size of the 6-way processor. More critically, the on-chip

cache hierarchy of the multiprocessor is signiﬁcantly different from the cache hierarchy of the

6-way superscalar processor. Each of the four cores has its own single-banked and single-ported

instruction and data caches, and each cache is scaled down by a factor of 4, to 8 KB. Since each

cache can only be accessed by a single processor’s single load/store unit, no additional overhead

is incurred to handle arbitration among independent memory access units. However, since the

four processors now share a single L2 cache, that cache requires extra latency to allow time for

interprocessor arbitration and crossbar delay.

These two microarchitectures were compared using nine small benchmarks that cover

a wide range of possible application classes. Table 1.2 shows the applications: two SPEC95

book Mobk089 October 26, 2007 10:22

12 CHIP MULTIPROCESSOR ARCHITECTURE

integer benchmarks (compress, m88ksim), one SPEC92 integer benchmark (eqntott), one other

integer application (MPsim), four SPEC95 ﬂoating point benchmarks (applu, apsi, swim,

tomcatv), and a multiprogramming application (pmake). The applications were parallelized

in different ways to run on the CMP microarchitecture. Compress was run unmodiﬁed on

both the SS and CMP microarchitectures, using only one processor of the CMP architecture.

Eqntott was parallelized manually by modifying a single bit vector comparison routine that is

responsible for 90% of the execution time of the application [5]. The CPU simulator (m88ksim)

was also parallelized manually into three “pipeline stage” threads. Each of the three threads

executes a different phase of simulating a different instruction at the same time. This style of

parallelization is very similar to the overlap of instruction execution that occurs in hardware

pipelining. The MPsim application was a Verilog model of a bus-based multiprocessor running

under a multithreaded compiled code simulator (Chronologic VCS-MT ). The multiple threads

were speciﬁed manually by assigning parts of the model hierarchy to different threads. The MP-

sim application used four closely coupled threads, one for each of the processors in the model.

The parallel versions of the SPEC95 ﬂoating point benchmarks were automatically generated

by the SUIF compiler system [6]. The pmake application was a program development work-

load that consisted of the compile phase of the Modiﬁed Andrew Benchmark [7]. The same

pmake application was executed on both microarchitectures; however, the OS was able to take

advantage of the extra processors in the MP microarchitecture to run multiple compilations in

parallel.

In order to simplify and speed simulation on this simple demonstration, these are older

benchmarks with relatively small data sets compared with those that would be used on real

machines today, such as the SPEC CPU 2006 suite [8]. To compensate, the caches and rest

of the memory hierarchy were scaled accordingly. For example, while a processor today would

tend to have an L2 cache of a few megabytes in size, our simulated systems have L2 caches of

only 256 KB. Given this memory system scaling and the fact that we are primarily interested

in the performance effects of the processor core architecture differences, the results from this

scaled-down simulation example should give a reasonable approximation of what would happen

on real systems with larger applications and better memory systems.

1.3.1 Simulation Results

Table 1.3 shows the IPC, branch prediction rates and cache miss rates for one processor of

the CMP, while Table 1.4 shows the instructions per cycle (IPC), branch prediction rates,

and cache miss rates for the SS microarchitecture. Averages are also presented (geometric for

IPC, arithmetic for the others). The cache miss rates are presented in the tables in terms of

misses per completed instruction (MPCI), including instructions that complete in kernel and user

mode. A key observation to note is that when the issue width is increased from 2 to 6 the

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