系统控制台：FPGA设计分析与调试全方位教程

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"ug_system_console"是一份详细的使用手册和教程，针对的是系统控制台（System Console）在FPGA设计中的应用。System Console作为一个强大的平台和工具，它的主要作用是提供对设计系统的全面洞察，这对于调试和缩短产品上市时间至关重要。它支持一系列高级任务： 1. 板级启动（Board Bring-up）：无论是最终完成还是部分完成的设计，System Console都能协助用户进行系统的初始化和故障排查，确保硬件设备的正确运行。 2. 远程调试（Remote Debugging）：只要有互联网连接，用户可以在任何地方通过System Console进行远程调试，极大地提高了调试的灵活性和效率。 3. 自动化测试与验证：借助System Console的脚本功能，用户可以编写复杂的脚本来跨多个设备执行运行时验证，简化了大规模测试流程。 4. 串行链路测试（Serial Link Testing）：Transceiver Toolkit提供了直观的图形界面，用户可以通过点击配置进行串行链路的细致测试和调优。 5. 内存接口调试（Memory Interface Debugging）：External Memory Interface Toolkit专门用于调试内存接口，帮助用户解决内存相关的问题。 6. 自定义IP集成（Custom Debug IP Integration）：System Console允许用户将自己的调试IP无缝集成到平台上，增强了设计的灵活性和扩展性。此外，资源还提供了在线培训课程和案例研究，以便用户深入学习System Console的各种用法和实际应用场景。通过这些教程、应用笔记和设计实例，用户可以学习如何利用System Console优化调试流程，提升设计质量和上市速度。System Console是一个综合性的调试工具，对于FPGA开发人员来说，掌握其使用方法是提高工作效率和产品质量的关键。

memory, then use claim_service to only access the address space between 0x0 and 0x1000. System Console

then allows other users to access other memory ranges, and denies access to the claimed memory range. The

claim_service command returns a newly created service path that you can use to access your claimed

resources.

You can access a service after you open it. When you finish accessing a service instance, use the close_service

command to direct System Console to make this resource available to other users.

Closing a Service Example

close_service master $claim_path; #Closes the service.

System Console Examples

Altera provides examples for performing board bring-up, creating a simple dashboard, and programming

a Nios II processor. The System_Console.zip file contains design files for the board bring-up example. The

Nios II Ethernet Standard .zip files contain the design files for the Nios II processor example.

The instructions for these examples assume that you are familiar with the Quartus II software, Tcl

commands, and Qsys.

Note:

Related Information

On-Chip Debugging Design Examples Website

Contains the design files for the example designs that you can download.

Board Bring-Up with System Console Tutorial

You can perform low-level hardware debugging of Qsys systems with System Console. You can debug systems

that include IP cores instantiated in your Qsys system or perform initial bring-up of your PCB. This board

bring-up tutorial uses a Nios II Embedded Evaluation Kit (NEEK) board and USB cable. If you have a

different development kit, you need to change the device and pin assignments to match your board and then

recompile the design.

Related Information

• Use Cases for System Console on page 10-1

• Faster Board Bring-Up with System Console Demo Video

Board Bring-Up Flow

1. Set up the board bring-up example.

2. Verify clock and reset signals.

3. Verify memory and other peripheral interfaces.

Analyzing and Debugging Designs with System Console

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Qsys Modules

Figure 10-3: Qsys Modules for Board Bring-up Example

The Qsys design for this example includes the following modules:

• JTAG to Avalon Master Bridge—Provides System Console host access to the memory-mapped IP in the

design via the JTAG interface.

• On-chip memory—Simplest type of memory for use in an FPGA-based embedded system. The memory

is implemented on the FPGA; consequently, external connections on the circuit board are not necessary.

• Parallel I/O (PIO) module—Provides a memory-mapped interface for sampling and driving general I/O

ports.

• Checksum Accelerator—Calculates the checksum of a data buffer in memory. The Checksum Accelerator

consists of the following:

• Checksum Calculator (checksum_transform.v)

• Read Master (slave.v)

• Checksum Controller (latency_aware_read_master.v)

Checksum Accelerator Functionality

The base address of the memory buffer and data length is passed to the Checksum Controller from a

memory-mapped master. The Read Master continuously reads data from memory and passes the data to

the Checksum Calculator. When the checksum calculations are complete, the Checksum Calculator issues

a valid signal along with the checksum result to the Checksum Controller. The Checksum Controller sets

the DONE bit in the status register and also asserts the interrupt signal. You should only read the result from

the Checksum Controller when the DONE bit and interrupt signal are asserted.

Setting Up the Board Bring-Up Design Example

To load the design example into the Quartus II software and program your device, follow these steps:

1. Unzip the System_Console.zip file to your local hard drive.

2. Click File > Open Project and select Systemconsole_design_example.qpf with the Quartus II software.

3. Change the device and pin assignments (LED, clock, and reset pins) in the Systemconsole_design_

example.qsf file to match your board.

4. Click Processing > Start Compilation

5. To Program your device, follow these steps:

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系统控制台：FPGA设计分析与调试全方位教程

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