Synopsys低功耗流用户指南

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"Synopsys Low-Power Flow User Guide - Synopsys公司2010年发布的低功耗设计流程用户指南，适用于IC设计中的电源优化。" Synopsys Low-Power Flow User Guide 是一份详细阐述Synopsys公司低功耗设计流程的文档，主要面向集成电路（IC）设计者和工程师，旨在帮助他们理解和实施有效的电源管理策略，以降低芯片在运行过程中的功耗。这份用户指南版本为D-2010.03，发布于2010年3月。低功耗设计在现代电子行业中变得至关重要，因为随着技术节点的不断缩小，芯片的功率密度增加，发热问题和电池寿命成为了设计的主要挑战。Synopsys Low-Power Flow提供了一整套方法学和工具，涵盖了设计的各个阶段，包括前端分析、设计实现、时序分析、功耗估计和签核等。该指南详细介绍了以下关键知识点： 1. **低功耗设计方法学**：涵盖多电压域设计、动态电压频率调整（DVFS）、睡眠模式设计、功耗门控以及静态和动态电源管理策略。 2. **Power Aware Design**：在设计早期就考虑到功耗，包括门级和RTL级的功耗分析，以及在设计规格阶段就进行功耗预算。 3. **Power Estimation and Analysis**：利用Synopsys的工具进行电源网络建模、开关活动分析、动态和漏电流估算，以获取准确的功耗数据。 4. **Power Optimization**：通过逻辑和物理优化技术降低功耗，如逻辑重新定时、门级电源门控、多阈值CMOS工艺选择等。 5. **Signoff Flow**：确保低功耗设计满足功能、性能和功耗的签核要求，包括完整的功耗签核流程和报告。 6. **Design Constraints and Sign-off**：定义和管理电源相关的约束，确保设计符合预期的功耗目标。 7. **知识产权（IP）集成与验证**：在低功耗设计中，IP模块的电源管理特性需要与系统级设计协调，指南将解释如何处理这个问题。 8. **工具集成**：Synopsys的低功耗解决方案通常包括一系列工具，如PrimeTime PX用于功耗分析，Design Compiler LP用于低功耗逻辑综合，PowerArtist用于电源架构设计等。这些工具之间的协同工作流程是用户需要理解和掌握的。 9. **案例研究和最佳实践**：通过实际案例来展示低功耗设计的实施步骤和技巧，以帮助工程师避免常见问题并提升效率。 10. **版权和许可**：Synopsys强调了软件和文档的版权保护，用户只能按照许可证协议的规定使用和复制这些资料，并且需要在副本上保留所有版权、商标、服务标记和专有权利通知。 Synopsys Low-Power Flow User Guide 是一个全面的参考资源，对于希望深入理解并应用低功耗设计技术的人来说，它是不可或缺的工具。通过遵循其中的指导，设计者可以有效地降低产品的功耗，提高能效，同时保持高性能和可靠性。

Chapter 1: Low-Power Design Strategies

Dynamic and Static Power 1-4

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Synopsys Low-Power Flow User Guide Version D-2010.03

Figure 1-2 Internal Power

Static (Leakage) Power

Leakage current was negligible in earlier CMOS technologies. However, with shrinking

device geometries and reduced threshold voltages, leakage power is becoming increasingly

significant, sometimes approaching the levels of dynamic power dissipation.

The main causes of leakage power are reverse-bias p-n junction diode leakage, sub-

threshold leakage, and gate leakage. These leakage paths in a CMOS inverter are shown

in Figure 1-3.

Figure 1-3 Static Leakage Currents

Intermediate

voltage

Short-circuit

(crowbar)

current

Off

Gate

leakage

p-n junction

leakage to

substrate

Sub-threshold

leakage

Off

Gate

leakage

p-n junction

leakage from

n-well

Sub-threshold

leakage

Chapter 1: Low-Power Design Strategies

Power Reduction Methods 1-5

Chapter 1: Low-Power Design Strategies

Power Reduction Methods 1-5

Synopsys Low-Power Flow User Guide Version D-2010.03

Leakage at reverse-biased p-n junctions (diode leakage) has always existed in CMOS

circuits. This is the leakage from the n-type drain of the NMOS transistor to the grounded p-

type substrate, and from the n-well (held at VDD) to the p-type drain of the PMOS transistor.

This leakage is relatively small.

Sub-threshold leakage is the small source-to-drain current that flows even when the

transistor is held in the “off” state. In older technologies, this current was negligible.

However, with lower power supply voltages and lower threshold voltages, “off” gate voltages

are getting close to “on” threshold voltages. Sub-threshold leakage current increases

exponentially as the gate voltage approaches the threshold voltage.

Gate leakage is the result of using an extremely thin insulating layer between the gate

conductor and the MOS transistor channel. Gate oxides are becoming so thin that only a

dozen or fewer layers of insulating atoms separate the gate from the source and drain.

Under these conditions, quantum-effect tunneling of electrons through the gate oxide can

occur, resulting in significant leakage from the gate to the source or drain.

Leakage currents occur whenever power is applied to the transistor, irrespective of the clock

speed or switching activity. Leakage cannot be reduced by slowing or stopping the clock.

However, it can be reduced or eliminated by lowering the supply voltage or by switching off

the power to the transistors entirely.

Power Reduction Methods

There are several different RTL and gate-level design strategies for reducing power. Some

methods, such as clock gating, have been used widely and successfully for many years.

Others, such as dynamic voltage and frequency scaling, have not been used much in the

past due to the difficultly of implementing them. As power becomes increasingly important

in advanced technologies, more methods are being exploited to achieve the design

requirements.

Supply Voltage Reduction

The most basic way to reduce power is to reduce the supply voltage. Power usage is

proportional to the square of the supply voltage, as the simple example in Figure 1-4

demonstrates. A 50 percent reduction in the supply voltage results in a 50 percent reduction

in current and a 75 percent reduction in power. A similar degree of power reduction can be

achieved in CMOS circuits for both dynamic and static power.

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