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首页TI TLIN1024A-Q1:高质量车载LIN收发器,支持20/100kbps数据传输
TI TLIN1024A-Q1:高质量车载LIN收发器,支持20/100kbps数据传输
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TI-TLIN1024A-Q1是一款专为汽车行业设计的四通道本地互连网络(LIN)收发器,它满足了AEC-Q100 Grade 1等级标准,确保在严苛的汽车环境中的可靠性和稳定性。这款产品兼容LIN 2.0、2.1、2.2和2.2A版本,以及ISO/DIS 17987-4电气物理层(EPL)规范,适用于车辆应用的LIN网络设计。 功能特性方面,TLIN1024A-Q1具有强大的功能安全支持,提供详细的文档供设计者在构建安全系统时参考。它能适应12伏电池供电环境,支持高达20kbps的数据发送速率和100kbps的数据接收速率,确保高效数据传输。该器件的供电范围广泛,可在4V到36V之间工作,特别强调了睡眠模式,通过超低电流消耗实现 LIN 总线唤醒或通过 EN 引脚进行本地唤醒。 为了优化功耗管理,LIN1024A-Q1集成了45kΩ的内置LIN拉高电阻,并能在上电和掉电过程中实现无毛刺操作,保证了LIN总线和RXD输出的平稳。此外,该器件具有多种保护机制,包括对±45V LIN总线故障的容忍、VSUP的欠电压保护、TXD主导状态超时保护(DTO)、热关断保护以及未供电节点或接地断开时的故障安全机制,确保系统的鲁棒性。 封装方面,TLIN1024A-Q1采用紧凑的3.5mm x 5.5mm VQFN封装,配合改进的自动化光学检查(AOI),提高了生产过程中的可检测性和可靠性。这款收发器是汽车电子系统设计的理想选择,提供了高性能、高可靠性和低功耗的解决方案,适用于各种LIN网络应用。
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7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃ ≤ T
A
≤ 125℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
D3
12V
Duty Cycle 3 (ISO/DIS 17987 Param
29)
(3)
TH
REC(MAX)
= 0.778 x V
SUP
, TH
DOM(MAX)
= 0.616 x V
SUP
, V
SUP
= 7 V to 18 V, t
BIT
= 96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2
x t
BIT
) (See Figure 8-10, Figure 8-11)
0.417
D3
12V
Duty Cycle 3
(3)
TH
REC(MAX)
= 0.645 x V
SUP
, TH
DOM(MAX)
= 0.616 x V
SUP
, V
SUP
= 4 V to 7 V, t
BIT
=
96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2 x
t
BIT
) (See Figure 8-10, Figure 8-11)
0.417
D3 Duty Cycle 3
(1)
(2)
TH
REC(MAX)
= 0.778 x V
SUP
TH
DOM(MAX)
= 0.616 x V
SUP
V
SUP
= 7 V to 18 V, t
BIT
= 96 μs
D3 = t
BUS_rec(min)
/(2 x t
BIT
) (See Figure
8-10, Figure 8-11)
0.417
D4
12V
Duty Cycle 4 (ISO/DIS 17987 Param
30)
(3)
TH
REC(MIN)
= 0.389 x V
SUP
, TH
DOM(MIN)
= 0.251 x V
SUP
, V
SUP
= 7 V to 18
V, t
BIT
= 96 µs (10.4 kbps), D4 =
t
BUS_rec(MAX)
/(2 x t
BIT
) (See Figure 8-10,
Figure 8-11)
0.59
D4
12V
Duty Cycle 4
(3)
TH
REC(MIN)
= 0.422 x V
SUP
, TH
DOM(MIN)
= 0.284 x V
SUP
, V
SUP
= 4 V to 7 V, t
BIT
=
96 µs (10.4 kbps), D4 = t
BUS_rec(MAX)
/(2
x t
BIT
) (See Figure 8-10, Figure 8-11)
0.59
D4 Duty Cycle 4
(1)
(2)
TH
REC(MIN)
= 0.389 x V
SUP
TH
DOM(MIN)
= 0.251 x V
SUP
V
SUP
= 7 V to 18 V, t
BIT
= 96 μs
D4 = t
BUS_rec(MAX)
/(2 x t
BIT
) (See Figure
8-10, Figure 8-11)
0.59
D1
LB
Duty cycle 1 at low battery
(1)
(2)
TH
REC(MAX)
= 0.665 x V
SUP
,
TH
DOM(MAX)
= 0.499 x V
SUP
,
V
SUP
= 5.5 V to 7 V, t
BIT
= 52 μs
0.396
D2
LB
Duty cycle 2 at low battery
(1)
(2)
TH
REC(MAX)
= 0.496 x V
SUP
TH
DOM(MAX)
= 0.361 x V
SUP
V
SUP
= 6.1 V to 7 V, t
BIT
= 52 μs
0.581
D3
LB
Duty cycle 3 at low battery
(1)
(2)
TH
REC(MAX)
= 0.665 x V
SUP
,
TH
DOM(MAX)
= 0.499 x V
SUP
,
V
SUP
= 5.5 V to 7 V, t
BIT
= 96 μs
0.396
D4
LB
Duty cycle 4 at low battery
(1)
(2)
TH
REC(MAX)
= 0.496 x V
SUP
TH
DOM(MAX)
= 0.361 x V
SUP
V
SUP
= 6.1 V to 7 V, t
BIT
= 96 μs
0.581
Tr-d max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Recessive to dominant
TH
REC(MAX)
= 0.744 x V
SUP
,
TH
DOM(MAX)
= 0.581 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 52 μs
t
REC(MAX)_D1
- t
DOM(MIN)_D1
10.8 µs
Td-r max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Dominant to recessive
TH
REC(MAX)
= 0.422 x V
SUP
,
TH
DOM(MAX)
= 0.284 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 52 μs
t
DOM(MAX)_D2
- t
REC(MIN)_D2
8.4 µs
Tr-d max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Recessive to dominant
TH
REC(MAX)
= 0.778 x V
SUP
TH
DOM(MAX)
= 0.616 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 96 μs
t
REC(MAX)_D3
- t
DOM(MIN)_D3
15.9 µs
Td-r max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Dominant to recessive
TH
REC(MIN)
= 0.389 x V
SUP
TH
DOM(MIN)
= 0.251 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 96 μs
t
DOM(MAX)_D4
- t
REC(MIN)_D4
17.28 µs
TLIN1024A-Q1
SLLSFF6 – SEPTEMBER 2021
www.ti.com
8 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLIN1024A-Q1
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7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃ ≤ T
A
≤ 125℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Tr-d max_low
Low battery transmitter propagation
delay timings for the duty cycle
(1)
(2)
Recessive to dominant
TH
REC(MAX)
= 0.665 x V
SUP
,
TH
DOM(MAX)
= 0.499 x V
SUP
5.5 V ≤ V
SUP
≤ 7 V, t
BIT
= 52 μs
t
REC(MAX)_low
- t
DOM(MIN)_low
10.8 µs
Td-r max_low
Low battery transmitter propagation
delay timings for the duty cycle
(1)
(2)
Dominant to recessive
TH
REC(MAX)
= 0.496 x V
SUP
TH
DOM(MAX)
= 0.361 x V
SUP
6.1 V ≤ V
SUP
≤ 7 V, t
BIT
= 52 μs
t
DOM(MAX)_low
- t
REC(MIN)_low
8.4 µs
(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩ and 899 pF/20 kΩ
(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ω and 899 pF/900 Ω
(3) ISO 17987 bus load conditions (C
LINBUS
, R
LINBUS
) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
7.8 Switching Characteristics
parameters valid across -40℃ ≤ T
A
≤ 125℃ (unless otherwise noted)
SYMBOL DESCRIPTION TEST CONDITIONS MIN NOM MAX UNIT
t
rx_pdr
Receiver rising propagation delay time
(ISO/DIS 17987 Param 31)
R
RXD
= 2.4 kΩ, C
RXD
= 20 pF
(See Figure 8-12 and Figure 8-13 )
6 µs
t
rx_pdf
Receiver falling propagation delay time
(ISO/DIS 17987 Param 31)
6 µs
t
rs_sym
Symmetry of receiver propagation delay
time
Rising edge with respect to falling edge,
(trx_sym = trx_pdf – trx_pdr), R
RXD
=
2.4 kΩ
,
C
RXD
= 20 pF (See Figure
8-12 and Figure 8-13 )
–2 2 µs
t
LINBUS
LIN wake-up time (Minimum dominant
time on LIN bus for wake-up)
See Figure 8-16, Figure 9-2, and Figure
9-3
25 100 150 µs
t
CLEAR
Time to clear false wake-up prevention
logic if LIN bus had a bus stuck
dominant fault (recessive time on LIN
bus to clear bus stuck dominant fault)
See Figure 9-3 8 17 50 µs
t
DST
Dominant state time out 20 34 80 ms
t
MODE_CHANGE
Mode change delay time
Time to change from standby mode to
normal mode or normal mode to sleep
mode through EN pin; See Figure 8-14
and Figure 9-4
2 15 µs
t
NOMINT
Normal mode initialization time
Time for normal mode to initialize and
data on RXD pin to be valid; See Figure
8-14
35 µs
t
PWR
Power up time
Upon power up time it takes for valid
data on RXD
1.5 ms
www.ti.com
TLIN1024A-Q1
SLLSFF6 – SEPTEMBER 2021
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TLIN1024A-Q1
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