7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃ ≤ T
A
≤ 125℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
D3
12V
Duty Cycle 3 (ISO/DIS 17987 Param
29)
(3)
TH
REC(MAX)
= 0.778 x V
SUP
, TH
DOM(MAX)
= 0.616 x V
SUP
, V
SUP
= 7 V to 18 V, t
BIT
= 96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2
x t
BIT
) (See Figure 8-10, Figure 8-11)
0.417
D3
12V
Duty Cycle 3
(3)
TH
REC(MAX)
= 0.645 x V
SUP
, TH
DOM(MAX)
= 0.616 x V
SUP
, V
SUP
= 4 V to 7 V, t
BIT
=
96 µs (10.4 kbps), D3 = t
BUS_rec(min)
/(2 x
t
BIT
) (See Figure 8-10, Figure 8-11)
0.417
D3 Duty Cycle 3
(1)
(2)
TH
REC(MAX)
= 0.778 x V
SUP
TH
DOM(MAX)
= 0.616 x V
SUP
V
SUP
= 7 V to 18 V, t
BIT
= 96 μs
D3 = t
BUS_rec(min)
/(2 x t
BIT
) (See Figure
8-10, Figure 8-11)
0.417
D4
12V
Duty Cycle 4 (ISO/DIS 17987 Param
30)
(3)
TH
REC(MIN)
= 0.389 x V
SUP
, TH
DOM(MIN)
= 0.251 x V
SUP
, V
SUP
= 7 V to 18
V, t
BIT
= 96 µs (10.4 kbps), D4 =
t
BUS_rec(MAX)
/(2 x t
BIT
) (See Figure 8-10,
Figure 8-11)
0.59
D4
12V
Duty Cycle 4
(3)
TH
REC(MIN)
= 0.422 x V
SUP
, TH
DOM(MIN)
= 0.284 x V
SUP
, V
SUP
= 4 V to 7 V, t
BIT
=
96 µs (10.4 kbps), D4 = t
BUS_rec(MAX)
/(2
x t
BIT
) (See Figure 8-10, Figure 8-11)
0.59
D4 Duty Cycle 4
(1)
(2)
TH
REC(MIN)
= 0.389 x V
SUP
TH
DOM(MIN)
= 0.251 x V
SUP
V
SUP
= 7 V to 18 V, t
BIT
= 96 μs
D4 = t
BUS_rec(MAX)
/(2 x t
BIT
) (See Figure
8-10, Figure 8-11)
0.59
D1
LB
Duty cycle 1 at low battery
(1)
(2)
TH
REC(MAX)
= 0.665 x V
SUP
,
TH
DOM(MAX)
= 0.499 x V
SUP
,
V
SUP
= 5.5 V to 7 V, t
BIT
= 52 μs
0.396
D2
LB
Duty cycle 2 at low battery
(1)
(2)
TH
REC(MAX)
= 0.496 x V
SUP
TH
DOM(MAX)
= 0.361 x V
SUP
V
SUP
= 6.1 V to 7 V, t
BIT
= 52 μs
0.581
D3
LB
Duty cycle 3 at low battery
(1)
(2)
TH
REC(MAX)
= 0.665 x V
SUP
,
TH
DOM(MAX)
= 0.499 x V
SUP
,
V
SUP
= 5.5 V to 7 V, t
BIT
= 96 μs
0.396
D4
LB
Duty cycle 4 at low battery
(1)
(2)
TH
REC(MAX)
= 0.496 x V
SUP
TH
DOM(MAX)
= 0.361 x V
SUP
V
SUP
= 6.1 V to 7 V, t
BIT
= 96 μs
0.581
Tr-d max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Recessive to dominant
TH
REC(MAX)
= 0.744 x V
SUP
,
TH
DOM(MAX)
= 0.581 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 52 μs
t
REC(MAX)_D1
- t
DOM(MIN)_D1
10.8 µs
Td-r max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Dominant to recessive
TH
REC(MAX)
= 0.422 x V
SUP
,
TH
DOM(MAX)
= 0.284 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 52 μs
t
DOM(MAX)_D2
- t
REC(MIN)_D2
8.4 µs
Tr-d max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Recessive to dominant
TH
REC(MAX)
= 0.778 x V
SUP
TH
DOM(MAX)
= 0.616 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 96 μs
t
REC(MAX)_D3
- t
DOM(MIN)_D3
15.9 µs
Td-r max
Transmitter propagation delay timings
for the duty cycle
(1)
(2)
Dominant to recessive
TH
REC(MIN)
= 0.389 x V
SUP
TH
DOM(MIN)
= 0.251 x V
SUP
7 V ≤ V
SUP
≤ 18 V, t
BIT
= 96 μs
t
DOM(MAX)_D4
- t
REC(MIN)_D4
17.28 µs
TLIN1024A-Q1
SLLSFF6 – SEPTEMBER 2021
www.ti.com
8 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: TLIN1024A-Q1
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