FPGA高级功耗估算与低功耗设计探索
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本文主要探讨了高级别FPGA（Field-Programmable Gate Array）的功耗估算与低功耗设计空间探索。作者Deming Chen，来自伊利诺伊大学厄巴纳-香槟分校电子与计算机工程系，针对Altera Stratix FPGA架构，该架构包含了通用逻辑元素、DSP核心和存储器等组件，提出了一个同步的资源分配和绑定算法，旨在优化FPGA的功耗。
在研究中，作者首先开发了一个针对该架构的高级别功耗估算器，其准确性是通过与商业级门级功耗估算工具Quartus II PowerPlay Analyzer进行比较来验证的。作者特别关注设计阶段中的互联和多路复用器，因为这些因素对功耗有显著影响。他们采用了创新的方法来探索设计空间，强调了资源分配和绑定在确定互联结构中的关键作用。
实验结果显示，作者的高级别功耗估算器与PowerPlay Analyzer的误差仅为8.7%，显示出较高的精度。此外，通过采用他们的算法，研究者成功实现了显著的功耗节省，具体节省的功率达到了320So。这一结果表明，高级别的功耗估算不仅能够提供快速的设计预估，而且在实际设计优化中具有实用价值，有助于工程师在早期阶段就做出更有效的低功耗决策。
在整个过程中，作者的策略涵盖了从系统级到硬件层面的综合考虑，包括但不限于逻辑布局、数据流管理和电源管理策略。通过这种高效率的估计方法，设计者可以在保证性能的同时，降低能耗，从而提高FPGA的整体能效比。这对于现代电子产品，尤其是在能源效率方面有着极高要求的应用领域来说，具有重要的实践意义。
5C-4
High-Level
Power
Estimation
and
Low-Power
Design
Space
Exploration
for
FPGAs
Deming
Chen
Department
of
ECE
University
of
Illinois,
Urbana-Champaign
dchenguiuc.edu
ABSTRACT
In
this
paper,
we
present
a
simultaneous
resource
allocation
and
binding
algorithm
for
FPGA
power
minimization.
To
fully
validate
our
methodology
and
result,
our
work
targets
a
real
FPGA
architecture
-
Altera
Stratix
FPGA
f2],
which
includes
generic
logic
elements,
DSP
cores,
and
memories,
etc.
We
design
a
high-
level
power
estimator
for
this
architecture
and
evaluate
its
estimation
accuracy
against
a
commercial
gate-level
power
estimator
Quartus
II
PowerPlay
Analyzer
f1].
During
the
synthesis
stage,
we
pay
special
attention
to
interconnections
and
multiplexers.
We
concentrate
on
resource
allocation
and
binding
tasks
because
they
are
the
key
steps
to
determine
the
interconnections.
We
use
a
novel
approach
to
explore
the
design
space.
Experimental
results
show
that
our
high-level
power
estimator
is
8.
7%
away
from
PowerPlay
Analyzer.
Meanwhile,
we
are
able
to
achieve
a
significant
amount
of
power
reduction
(320So)
with
better
circuit
speed
(1600)
compared
to
a
traditional
resource
allocation
and
binding
algorithm.
1.
INTRODUCTION
The
basic
problem
of
high-level
synthesis
is
the
mapping
of
a
behavioral
description
of
a
digital
system
into
an
RTL
design
consisting
of
a
datapath
and
a
control
unit.
A
datapath
is
composed
of
three
types
of
components:
functional
units
(e.g.,
ALUs,
multipliers,
and
shifters),
storage
units
(e.g.,
registers
and
memory),
and
interconnection
units
(e.g.,
buses
and
multiplexers).
The
control
unit
is
specified
as
a
finite
state
machine,
which
controls
the
set
of
operations
for
the
datapath
to
perform
during
every
control
step.
The
high-level
synthesis
process
mainly
consists
of
three
subtasks:
scheduling,
allocation,
and
binding.
Scheduling
determines
when
a
computational
operation
will
be
executed;
allocation
determines
how
many
instances
of
resources
(functional
units,
registers,
or
interconnection
units)
are
needed;
binding
binds
operations,
variables,
or
data
transfers
to
these
resources.
Traditionally,
people
are
more
concerned
with
area
and
power
of
functional
units
and
registers.
As
technology
advances,
the
area
and
power
of
multiplexers
and
interconnects
have
by
far
outweighed
the
area
and
power
of
functional
units
and
registers,
especially
for
FPGA
architectures.
Studies
show
that
interconnects
contribute
70-
80%
of
the
total
area
[27]
and
75-85%
of
the
total
power
[19][20]
in
FPGAs.
Multiplexers
are
particularly
expensive
for
FPGA
architectures.
It
is
shown
that
the
delay
and
power
data
of
a
32-to-I
multiplexer
are
almost
equivalent
to
a
18-bit
multiplier
in
0.lum
technology
in
FPGA
designs
[6][7].
In
general,
smaller
number
of
functional
units
or
registers
allocated
but
with
larger
number
of
wide
multiplexers
and
larger
amount
of
interconnects
may
lead
to
a
completely
unfavorable
solution
for
both
performance
and
power.
To
tackle
this
increasingly
alarming
problem,
it
will
require
an
efficient
search
engine
to
explore
a
sufficiently
large
solution
space
considering
multiple
constraining
factors,
such
as
resource
allocation
and
binding,
MUX
generation,
and
interconnection
generation,
for
optimizing
performance
or
power,
or
study
the
tradeoff
between
them.
Jason
Cong,
Yiping
Fan,
Zhiru
Zhang
Computer
Science
Department
University
of
California,
Los
Angeles
{cong,
fanyp,
zhiruz}gcs.ucla.edu
Although
low-power
high-level
synthesis
for
ASICs
is
an
old
topic,
high-level
synthesis
for
FPGA
power
minimization
has
not
been
widely
studied.
We
are
only
aware
of
one
previous
work
[7],
where
the
optimization
goal
is
to
minimize
power
of
FPGA
designs
under
performance/latency
constraints.
The
authors
adopted
a
simulated
annealing-based
algorithm,
which
carried
out
high-level
synthesis
subtasks
simultaneously.
However,
the
delay
model
in
[7]
did
not
consider
multiplexer
delay,
which
could
represent
a
significant
portion
of
the
critical
path
delay
for
FPGA
chips.
Also,
[7]
only
worked
on
data-flow
graphs
(DFGs),
and
it
did
not
model
existing
commercial
FPGAs.
In
this
work
we
present
a
novel
design
space
exploration
engine,
xPlore-Power,
for
FPGA
power
minimization.
We
concentrate
on
resource
allocation
and
binding
tasks
because
they
are
the
key
steps
to
determine
the
interconnections
during
high-level
synthesis.
To
fully
validate
our
methodology
and
result,
we
target
a
real
FPGA
architecture
Altera
Stratix
architecture
[2],
which
includes
generic
logic
elements,
DSP
cores,
and
different
types
of
memories,
etc.
We
design
a
high-level
power
estimator
for
this
architecture
and
verify
that
its
power
estimation
result
is
very
close
to
that
reported
by
Altera's
gate-level
power
estimator
Quartus
II
PowerPlay
Analyzer
[1].
We
form,
propagate
and
prune
binding/allocation
solution
points
guided
by
our
power
and
delay
estimation.
During
this
process,
we
pay
attention
to
interconnects
and
multiplexers
to
control
their
power
consumption
and
delay.
Eventually,
we
generate
a
design
solution
curve,
which
can
provide
ideal
solution
points
with
low
power
and
high
performance.
The
rest
of
this
paper
is
organized
as
follows.
In
Section
2
we
present
related
work.
Section
3
provides
definitions
and
problem
formulation.
Section
4
presents
CDFG
simulation,
and
power
and
delay
estimation.
Section
5
presents
detailed
description
of
our
xPlore-Power
algorithm.
Section
6
presents
experimental
results,
and
Section
7
concludes
this
paper.
2.
RELATED
WORK
There
is
extensive
literature
on
binding
and
allocation
problems
for
high-level
synthesis
[10][11].
The
previous
work
can
be
roughly
categorized
into
two
major
groups.
The
first
group
solves
register
binding
and
functional
unit
binding
separately.
Representative
algorithms
include
clique
partitioning
[28],
weighted
bipartite-
matching
[15],
network
flow
[5][12],
and
k-cofamily
[6].
The
challenge
for
these
approaches
is
how
to
achieve
global
optimization.
The
second
group
tries
to
address
the
global
optimality
and
performs
simultaneous
functional
unit
and
register
binding.
Representative
algorithms
include
simulated
annealing
[7][8][18],
simulated
evolution
[21],
and
ILP
(integer
linear
programming)
[13][26].
Since
the
subtasks
of
high-level
synthesis
are
highly
interrelated,
simultaneous
optimization
approaches
try
to
consider
all
the
involved
optimization
parameters
together
and
explore
the
combined
solution
space
for
overall
better
results.
One
concern
for
these
algorithms
is
their
scalability
towards
optimizing
large
designs.
There
is
some
work
that
carries
out
simultaneous
optimization
one
control
step
at
a
time
[16][23].
Although
this
approach
may
have
better
runtime,
it
could
lose
the
global
optimization
opportunity
1-4244-0630-7/07/$20.00
c
2007
IEEE.
529
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