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首页ADSP-BF70x黑鳍处理器编程参考手册
本资源是针对ADSP-BF70x系列Blackfin处理器的编程参考手册,由Analog Devices, Inc.于2016年10月发布,编号为82-100123-01。该手册详细介绍了BF70x处理器的寄存器结构、功能和编程指南,是进行该处理器开发和调试的重要文档。
首先,ADSP-BF7xx Blackfin+Processor是基于Blackfin架构的高性能数字信号处理器,专为实时信号处理应用设计。这些处理器以其低功耗、高精度和灵活的内核设计而闻名,适用于音频、视频、通信和工业控制等领域。
手册的核心内容包括但不限于:
1. 寄存器概述:这部分详细列出了BF70x处理器的所有寄存器及其功能,如控制寄存器、状态寄存器、配置寄存器等,帮助开发者理解处理器内部的工作原理,并指导如何通过编程访问和修改这些寄存器。
2. 编程接口:手册提供了API和指令集的详细介绍,包括汇编语言和高级语言(如C/C++)的编程接口,以便程序员根据项目需求选择合适的编程方式。
3. 硬件描述:包括引脚分配、内存映射和系统架构图,这对于理解和连接外部设备以及设计嵌入式系统至关重要。
4. 异常处理和中断管理:BF70x支持多种中断源,手册解释了中断的触发条件、优先级管理和响应机制,确保系统的稳定性和实时性。
5. 电源管理和时钟配置:这部分阐述了处理器的电源管理模式和时钟配置选项,帮助优化功耗和性能。
6. 安全性和加密:手册可能涉及处理器的固件安全特性,如代码保护和数据加密,对于保护知识产权和防止非法修改至关重要。
7. 版权和免责声明:手册明确指出所有内容受版权保护,未经许可不得复制或再版。此外,ADI公司不承担因使用手册内容导致的专利侵权或其他第三方权利侵犯的责任,同时也提醒用户没有被默示授予专利使用权。
8. 商标和服务标记声明:列举了ADI公司的注册商标和品牌标识,提示读者区分官方资料和非官方资源。
通过阅读和研究这份编程参考手册,开发人员可以深入理解ADSP-BF70x处理器的工作机制,从而更有效地开发出高效、稳定的软件应用程序。同时,手册还强调了在使用过程中尊重知识产权和遵守法律义务的重要性。
32 x 32-Bit Multiply, Integer (MultInt)................................................................................................. 8–86
Dual 16 x 16-Bit MAC (ParaMac16AndMac16) ................................................................................... 8–87
Dual 16 x 16-Bit MAC with Move to Register (ParaMac16AndMac16WithMv) .................................. 8–88
Dual 16 x 16-Bit MAC with Move to Register (ParaMac16WithMvAndMac16) .................................. 8–89
Dual 16 x 16-Bit MAC with Moves to Registers (ParaMac16WithMvAndMac16WithMv) .................. 8–90
Dual 16 x 16-Bit MAC with Move to Register (ParaMac16AndMv) ..................................................... 8–91
Dual 16 x 16-Bit MAC with Moves to Registers (ParaMac16WithMvAndMv)..................................... 8–92
Dual 16 x 16-Bit Multiply (ParaMult16AndMult16) ............................................................................ 8–93
Dual Move to Register and 16 x 16-Bit MAC (ParaMvAndMac16) ......................................................8–94
Dual Move to Register and 16 x 16-Bit MAC with Move to Register (ParaMvAndMac16WithMv)...... 8–95
Pointer Math Operations.......................................................................................................................... 8–96
32-bit Add or Subtract (DagAdd32)......................................................................................................8–97
32-bit Add or Subtract Constant (DagAddImm) ................................................................................... 8–98
32-bit Add then Shift (DagAddSubShift) .............................................................................................. 8–99
32-bit Add Shifted Pointer (PtrOp)..................................................................................................... 8–100
Pointer Logical Shift (LShiftPtr).......................................................................................................... 8–101
Rotate Operations .................................................................................................................................. 8–101
32-Bit Rotate (Shift_Rot32)................................................................................................................ 8–102
Accumulator Rotate (Shift_RotAcc) .................................................................................................... 8–103
Shift Operations ..................................................................................................................................... 8–104
16-Bit Arithmetic Shift (AShift16) ...................................................................................................... 8–105
Vectored 16-Bit Arithmetic (AShift16Vec)........................................................................................... 8–108
32-Bit Arithmetic Shift (AShift32) ...................................................................................................... 8–110
Accumulator Arithmetic Shift (AShiftAcc)........................................................................................... 8–113
16-Bit Logical Shift (LShift16)............................................................................................................ 8–115
Vectored 16-Bit Logical Shift (LShift16Vec) ........................................................................................8–117
32-Bit Logical Shift (LShift)................................................................................................................ 8–119
Accumulator Logical Shift (LShiftA) ................................................................................................... 8–121
Sequencer Instructions............................................................................................................................... 8–123
Branch Operations ................................................................................................................................. 8–124
Conditional Jump Immediate (BrCC)................................................................................................. 8–125
ADSP-BF7xx Blackfin+ Processor
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Jump (Jump) ....................................................................................................................................... 8–126
Jump Immediate (JumpAbs)................................................................................................................ 8–127
Call (Call)............................................................................................................................................ 8–128
Return from Branch (Return).............................................................................................................. 8–129
Hardware Loop Set Up (LoopSetup) ................................................................................................... 8–130
Control Code Bit Management Operations............................................................................................ 8–134
Compute Move CC to a D Register (CCToDreg)................................................................................ 8–134
Move CC To/From ASTAT (CCToStat16) .......................................................................................... 8–135
Move Status to CC (MvToCC)............................................................................................................ 8–136
Move Status to CC (MvToCC_STAT).................................................................................................8–137
32-Bit Pointer Register Compare and Set CC (CCFlagP).................................................................... 8–138
Accumulator Compare and Set CC (CompAccumulators)................................................................... 8–139
32-Bit Register Compare and Set CC (CompRegisters)....................................................................... 8–140
Event Management Operations .............................................................................................................. 8–142
Interrupt Control (IMaskMv) ............................................................................................................. 8–142
Sequencer Mode (Mode) ..................................................................................................................... 8–143
Raise Interrupt (Raise) ........................................................................................................................ 8–144
Stack Operations .................................................................................................................................... 8–145
Linkage (Linkage)................................................................................................................................ 8–146
Stack Pop (Pop) ................................................................................................................................... 8–148
Stack Push (Push)................................................................................................................................ 8–150
Stack Push/Pop Multiple Registers (PushPopMul16) .......................................................................... 8–151
Synchronization Operations ................................................................................................................... 8–155
Cache Control (CacheCtrl)..................................................................................................................8–155
Sync (Sync).......................................................................................................................................... 8–157
SyncExcl (SyncExcl)............................................................................................................................. 8–160
NOP (NOP) ....................................................................................................................................... 8–160
32-Bit No Operation (NOP32)........................................................................................................... 8–161
TestSet (TestSet).................................................................................................................................. 8–162
Memory or Pointer Instructions ................................................................................................................ 8–163
Load from Immediate (Value) Operations .............................................................................................. 8–163
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ADSP-BF7xx Blackfin+ Processor
Accumulator Register Initialization (LdImmToAx).............................................................................. 8–164
32-Bit Accumulator Register (.w) Initialization (LdImmToAxW)........................................................ 8–164
32-Bit Accumulator Register (.x) Initialization (LdImmToAxX).......................................................... 8–165
16-Bit Register Initialization (LdImmToDregHL)............................................................................... 8–166
32-Bit Register Initialization (LdImmToReg)...................................................................................... 8–167
Dual Accumulator 0 and 1 Registers Initialization (LdImmToAxDual) ............................................... 8–168
Memory Load Operations ......................................................................................................................8–169
8-Bit Load from Memory to 32-bit Register (LdM08bitToDreg) ........................................................ 8–169
16-Bit Load from Memory to 32-Bit Register (LdM16bitToDreg)......................................................8–170
16-Bit Load from Memory (LdM16bitToDregH) ............................................................................... 8–173
16-Bit Load from Memory (LdM16bitToDregL) ................................................................................ 8–175
32-Bit Load from Memory (LdM32bitToDreg)................................................................................... 8–177
32-Bit Pointer Load from Memory (LdM32bitToPreg) ....................................................................... 8–180
Memory Load (Exclusive) Operations..................................................................................................... 8–181
8-Bit Load from Memory to 32-bit Register (LdX08bitToDreg) ......................................................... 8–182
16-Bit Load from Memory to 32-Bit Register (LdX16bitToDreg)....................................................... 8–183
16-Bit Load from Memory (LdX16bitToDregH) ................................................................................ 8–183
16-Bit Load from Memory (LdX16bitToDregL) ................................................................................. 8–184
32-Bit Load from Memory (LdX32bitToDreg).................................................................................... 8–184
Pack Operations ..................................................................................................................................... 8–185
Pack 8-Bit to 32-Bit (BytePack)........................................................................................................... 8–185
Spread 8-Bit to 16-Bit (ByteUnPack)................................................................................................... 8–186
Pack 16-Bit to 32-Bit (Pack16Vec) ...................................................................................................... 8–189
Memory Store Operations ...................................................................................................................... 8–190
16-Bit Store to Memory (StDregHToM16bit)..................................................................................... 8–190
16-Bit Store to Memory (StDregLToM16bit) ...................................................................................... 8–192
8-Bit Store to Memory (StDregToM08bit).......................................................................................... 8–194
32-Bit Store to Memory (StDregToM32bit)........................................................................................ 8–195
Store Pointer (StPregToM32bit).......................................................................................................... 8–198
Memory Store (Exclusive) Operations..................................................................................................... 8–199
16-Bit Store to Memory (StDregHToX16bit)...................................................................................... 8–201
16-Bit Store to Memory (StDregLToX16bit) ....................................................................................... 8–202
ADSP-BF7xx Blackfin+ Processor
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8-Bit Store to Memory (StDregToX08bit)........................................................................................... 8–203
32-Bit Store to Memory (StDregToX32bit)......................................................................................... 8–203
Specialized Compute Instructions.............................................................................................................. 8–204
Block Floating Point Operations............................................................................................................. 8–205
Exponent Detection (Shift_ExpAdj32) ................................................................................................ 8–205
DCT Operations .................................................................................................................................... 8–207
32-Bit Prescale Up Add/Sub to 16-bit (AddSubRnd12)....................................................................... 8–207
32-Bit Prescale Down Add/Sub to 16-Bit (AddSubRnd20) ................................................................. 8–208
Divide Operations .................................................................................................................................. 8–209
DIVS and DIVQ Divide Primitives (Divide)....................................................................................... 8–210
Linear Feedback Shift Register LFSR Operations ................................................................................... 8–213
40-Bit BXOR LSFR with Feedback to a Register (BXOR)................................................................... 8–213
40-Bit BXORShift LSFR with Feedback to the Accumulator (BXORShift_NF).................................. 8–219
32-Bit BXOR or BXORShift LSFR without Feedback (BXOR_NF) ................................................... 8–220
Video Operations ...................................................................................................................................8–220
Vectored 8-Bit to 16-Bit Add then Clip to 8-Bit (Byteop3P) (AddClip) .............................................. 8–221
Vectored 8-Bit Add or Subtract to 16-Bit (Byteop16P/M) (AddSub4x8) ............................................. 8–223
Disable Alignment Exception (DisAlignExcept) .................................................................................. 8–225
Byte Align (Shift_Align) ...................................................................................................................... 8–226
Quad Byte Average (Byteop2P) (Avg4x8Vec)....................................................................................... 8–227
Vector Byte Average (Byteop1P) (Avg8Vec) ......................................................................................... 8–230
Dual Accumulator Extraction with Addition (AddAccHalf) ................................................................ 8–233
Vectored 8-Bit Sum of Absolute Differences (SAD8Vec)...................................................................... 8–234
Viterbi Operations.................................................................................................................................. 8–236
16-Bit Add on Sign (AddOnSign) ....................................................................................................... 8–236
Dual 16-Bit Modulo Maximum with History (Shift_DualVitMax)..................................................... 8–238
16-Bit Modulo Maximum with History (Shift_VitMax) .....................................................................8–239
Instruction Page Tables.............................................................................................................................. 8–243
ALU Binary Operations (ALU2op)......................................................................................................... 8–243
Conditional Branch PC relative on CC (BrCC)...................................................................................... 8–244
Move CC conditional bit, to and from dreg (CC2Dreg)......................................................................... 8–245
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ADSP-BF7xx Blackfin+ Processor
Copy CC conditional bit, from status (CC2Stat).................................................................................... 8–246
CBIT................................................................................................................................................... 8–246
Set CC conditional bit (CCFlag) ............................................................................................................8–247
Conditional Move (CCMV) ...................................................................................................................8–249
GDST ................................................................................................................................................. 8–249
GSRC.................................................................................................................................................. 8–250
Cache Control (CacheCtrl)..................................................................................................................... 8–250
PREGA ............................................................................................................................................... 8–250
Call function with pcrel address (CallA) ................................................................................................. 8–251
Compute with 3 operands (Comp3op)................................................................................................... 8–251
Destructive Binary Operations, dreg with 7bit immediate (CompI2opD) .............................................. 8–252
Destructive Binary Operations, preg with 7bit immediate (CompI2opP)............................................... 8–253
DAG Arithmetic (DAGModIk) .............................................................................................................. 8–253
DAG Arithmetic (DAGModIm) ............................................................................................................. 8–254
ALU Operations (Dsp32Alu).................................................................................................................. 8–255
A0_HL................................................................................................................................................ 8–259
A1_HL................................................................................................................................................ 8–260
AOPL.................................................................................................................................................. 8–260
DDST0_HL........................................................................................................................................ 8–260
DSRC0_HL ........................................................................................................................................ 8–260
NSAT .................................................................................................................................................. 8–261
PAIR0 ................................................................................................................................................. 8–261
PAIR1 ................................................................................................................................................. 8–261
RS ....................................................................................................................................................... 8–261
RSC..................................................................................................................................................... 8–262
SAT ..................................................................................................................................................... 8–262
SAT2 ................................................................................................................................................... 8–262
SMODE.............................................................................................................................................. 8–262
SX ....................................................................................................................................................... 8–263
SXA..................................................................................................................................................... 8–263
XMODE ............................................................................................................................................. 8–264
ADSP-BF7xx Blackfin+ Processor
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