Philips Semiconductors
LPC2194
Single-chip 16/32-bit microcontrollers
Preliminary data Rev. 01 — 06 February 2004 7 of 33
9397 750 12757
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
P0.27 11 I AIN0 — A/D converter, input 0. This analog input is always connected to its
pin.
I CAP0.1 — Capture input for Timer0, channel 1.
O MAT0.1 — Match output for Timer0, channel 1.
P0.28 13 I AIN1 — A/D converter, input 1. This analog input is always connected to its
pin.
I CAP0.2 — Capture input for Timer0, channel 2.
O MAT0.2 — Match output for Timer0, channel 2.
P0.29 14 I AIN2 — A/D converter, input 2. This analog input is always connected to its
pin.
I CAP0.3 — Capture input for Timer0, Channel 3.
O MAT0.3 — Match output for Timer0, channel 3.
P0.30 15 I AIN3 — A/D converter, input 3. This analog input is always connected to its
pin.
I EINT3 — External interrupt 3 input.
I CAP0.0 — Capture input for Timer0, channel 0.
P1.0 to P1.31 16, 12, 8, 4,
48, 44, 40,
36, 32, 28,
24, 64, 60,
56, 52, 20
I/O Port 1: Port 1 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 1 pins depends upon the pin
function selected via the Pin Connect Block. Pins 0 through 15 of port 1 are
not available.
P1.16 16 O TRACEPKT0 — Trace Packet, bit 0. Standard I/O port with internal pull-up.
P1.17 12 O TRACEPKT1 — Trace Packet, bit 1. Standard I/O port with internal pull-up.
P1.18 8 O TRACEPKT2 — Trace Packet, bit 2. Standard I/O port with internal pull-up.
P1.19 4 O TRACEPKT3 — Trace Packet, bit 3. Standard I/O port with internal pull-up.
P1.20 48 O TRACESYNC — Trace Synchronization. Standard I/O port with internal
pull-up.
Note: LOW on this pin while
RESET is LOW, enables pins P1.25:16 to
operate as Trace port after reset.
P1.21 44 O PIPESTAT0 — Pipeline Status, bit 0. Standard I/O port with internal pull-up.
P1.22 40 O PIPESTAT1 — Pipeline Status, bit 1. Standard I/O port with internal pull-up.
P1.23 36 O PIPESTAT2 — Pipeline Status, bit 2. Standard I/O port with internal pull-up.
P1.24 32 O TRACECLK — Trace Clock. Standard I/O port with internal pull-up.
P1.25 28 I EXTIN0 — External Trigger Input. Standard I/O with internal pull-up.
P1.26 24 I/O RTCK — Returned Test Clock output. Extra signal added to the JTAG port.
Assists debugger synchronization when processor frequency varies.
Bi-directional pin with internal pull-up.
Note: LOW on this pin while
RESET is LOW, enables pins P1.31:26 to
operate as Debug port after reset.
P1.27 64 O TDO — Test Data out for JTAG interface.
P1.28 60 I TDI — Test Data in for JTAG interface.
P1.29 56 I TCK — Test Clock for JTAG interface.
P1.30 52 I TMS — Test Mode Select for JTAG interface.
P1.31 20 I
TRST — Test Reset for JTAG interface.
Table 3: Pin description
…continued
Symbol Pin Type Description