Intel® 64及IA-32架构手册：指令集参考（第2卷）

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"《Intel® 64和IA-32架构手册：卷2B：指令集参考》是Intel针对64位和IA-32架构软件开发者的权威指南，由九个卷本组成。此文档特别关注的是指令集参考部分，编号为253667。它详尽地介绍了这些架构的底层细节，包括处理器的指令集、操作码以及系统编程的指导原则。该手册的编写目的是为了帮助开发者深入理解并利用Intel处理器的强大功能，进行高效能的应用程序设计和优化。它涵盖了Intel 64和IA-32架构的基础架构信息，包括处理器的体系结构特性、内存管理、多媒体处理、并发性支持等关键元素。每个指令都有详细的描述，包括其目的、操作数类型、语法、执行行为和可能产生的结果，这对于程序员来说是不可或缺的参考资料。在使用这份手册时，开发者需要注意，Intel 64和IA-32架构的优势取决于具体的系统配置，可能需要硬件支持、特定软件的激活或者服务。因此，在评估设计需求时，应参考所有九个卷本的内容，确保技术选型与实际环境相匹配。此外，手册强调了安全性的考虑，指出没有绝对安全的计算机系统，Intel也不承担因数据丢失或系统损坏造成的任何责任。因此，开发者在开发过程中要充分考虑安全措施和备份策略。最后，手册指出，未经许可，用户不得使用或协助未经授权的活动，这体现了Intel对于知识产权的尊重和保护。《Instruction Set Reference M-U》是整个系列中的一个重要组成部分，为软件开发者提供了深入了解和利用Intel处理器的强大工具，对于从事系统级编程、性能优化或高级应用开发的工程师来说，这是一份不可或缺的技术宝典，发布日期为2016年12月，适用于美国市场。"

MAXPD—Maximum of Packed Double-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

4-14 Vol. 2B

MAXPD (128-bit Legacy SSE version)

DEST[63:0] MAX(DEST[63:0], SRC[63:0])

DEST[127:64] MAX(DEST[127:64], SRC[127:64])

DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent

VMAXPD __m512d _mm512_max_pd( __m512d a, __m512d b);

VMAXPD __m512d _mm512_mask_max_pd(__m512d s, __mmask8 k, __m512d a, __m512d b,);

VMAXPD __m512d _mm512_maskz_max_pd( __mmask8 k, __m512d a, __m512d b);

VMAXPD __m512d _mm512_max_round_pd( __m512d a, __m512d b, int);

VMAXPD __m512d _mm512_mask_max_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);

VMAXPD __m512d _mm512_maskz_max_round_pd( __mmask8 k, __m512d a, __m512d b, int);

VMAXPD __m256d _mm256_mask_max_pd(__m5256d s, __mmask8 k, __m256d a, __m256d b);

VMAXPD __m256d _mm256_maskz_max_pd( __mmask8 k, __m256d a, __m256d b);

VMAXPD __m128d _mm_mask_max_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);

VMAXPD __m128d _mm_maskz_max_pd( __mmask8 k, __m128d a, __m128d b);

VMAXPD __m256d _mm256_max_pd (__m256d a, __m256d b);

(V)MAXPD __m128d _mm_max_pd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions

Invalid (including QNaN Source Operand), Denormal

Other Exceptions

Non-EVEX-encoded instruction, see Exceptions Type 2.

EVEX-encoded instruction, see Exceptions Type E2.

MAXPS—Maximum of Packed Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, M-U

Vol. 2B 4-15

MAXPS—Maximum of Packed Single-Precision Floating-Point Values

Instruction Operand Encoding

Description

Performs a SIMD compare of the packed single-precision floating-point values in the first source operand and the

second source operand and returns the maximum value for each pair of values to the destination operand.

If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is

returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that

is, a QNaN version of the SNaN is not returned).

If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN

or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source

operand (from either the first or second operand) be returned, the action of MAXPS can be emulated using a

sequence of instructions, such as, a comparison followed by AND, ANDN and OR.

EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second

source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector

broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally

updated with writemask k1.

VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM

of the corresponding ZMM register destination are zeroed.

VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM

of the corresponding ZMM register destination are zeroed.

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-

nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding

ZMM register destination are unmodified.

Opcode/

Instruction

Op /

64/32

bit Mode

Support

CPUID

Feature

Flag

Description

0F 5F /r

MAXPS xmm1, xmm2/m128

RM V/V SSE Return the maximum single-precision floating-point values

between xmm1 and xmm2/mem.

VEX.NDS.128.0F.WIG 5F /r

VMAXPS xmm1, xmm2,

xmm3/m128

RVM V/V AVX Return the maximum single-precision floating-point values

between xmm2 and xmm3/mem.

VEX.NDS.256.0F.WIG 5F /r

VMAXPS ymm1, ymm2,

ymm3/m256

RVM V/V AVX Return the maximum single-precision floating-point values

between ymm2 and ymm3/mem.

EVEX.NDS.128.0F.W0 5F /r

VMAXPS xmm1 {k1}{z}, xmm2,

xmm3/m128/m32bcst

FV V/V AVX512VL

AVX512F

Return the maximum packed single-precision floating-point

values between xmm2 and xmm3/m128/m32bcst and store

result in xmm1 subject to writemask k1.

EVEX.NDS.256.0F.W0 5F /r

VMAXPS ymm1 {k1}{z}, ymm2,

ymm3/m256/m32bcst

FV V/V AVX512VL

AVX512F

Return the maximum packed single-precision floating-point

values between ymm2 and ymm3/m256/m32bcst and store

result in ymm1 subject to writemask k1.

EVEX.NDS.512.0F.W0 5F /r

VMAXPS zmm1 {k1}{z}, zmm2,

zmm3/m512/m32bcst{sae}

FV V/V AVX512F Return the maximum packed single-precision floating-point

values between zmm2 and zmm3/m512/m32bcst and store

result in zmm1 subject to writemask k1.

Op/En Operand 1 Operand 2 Operand 3 Operand 4

RM ModRM:reg (r, w) ModRM:r/m (r) NA NA

RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA

FV ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA

MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value

INSTRUCTION SET REFERENCE, M-U

4-18 Vol. 2B

MAXSD—Return Maximum Scalar Double-Precision Floating-Point Value

Instruction Operand Encoding

Description

Compares the low double-precision floating-point values in the first source operand and the second source

operand, and returns the maximum value to the low quadword of the destination operand. The second source

operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM

registers. When the second source operand is a memory operand, only 64 bits are accessed.

If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If

a value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a

QNaN version of the SNaN is not returned).

If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid

floating-point value, is written to the result. If instead of this behavior, it is required that the NaN of either source

operand be returned, the action of MAXSD can be emulated using a sequence of instructions, such as, a comparison

followed by AND, ANDN and OR.

128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the

corresponding destination register remain unchanged.

VEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding

bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.

EVEX encoded version: The low quadword element of the destination operand is updated according to the

writemask.

Software should ensure VMAXSD is encoded with VEX.L=0. Encoding VMAXSD with VEX.L=1 may encounter unpre-

dictable behavior across different processor generations.

Opcode/

Instruction

Op /

64/32

bit Mode

Support

CPUID

Feature

Flag

Description

F2 0F 5F /r

MAXSD xmm1, xmm2/m64

RM V/V SSE2 Return the maximum scalar double-precision floating-point

value between xmm2/m64 and xmm1.

VEX.NDS.128.F2.0F.WIG 5F /r

VMAXSD xmm1, xmm2,

xmm3/m64

RVM V/V AVX Return the maximum scalar double-precision floating-point

value between xmm3/m64 and xmm2.

EVEX.NDS.LIG.F2.0F.W1 5F /r

VMAXSD xmm1 {k1}{z}, xmm2,

xmm3/m64{sae}

T1S V/V AVX512F Return the maximum scalar double-precision floating-point

value between xmm3/m64 and xmm2.

Op/En Operand 1 Operand 2 Operand 3 Operand 4

RM ModRM:reg (r, w) ModRM:r/m (r) NA NA

RVM ModRM:reg (w) VEX.vvvv ModRM:r/m (r) NA

T1S ModRM:reg (w) EVEX.vvvv ModRM:r/m (r) NA

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Intel® 64及IA-32架构手册：指令集参考（第2卷）

Intel® 64 and IA-32 Architectures Software Developer’s Manual

Intel 64 and IA-32 Architectures Software Developer's Manual Volume 1---Volume 3

Intel® 64 and IA-32 Architectures Software Developer's Manuals

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